XPM_NMU_STRM - 2025.1 English - Parameterized Macro: AXI Streaming (AXI Full) NOC Master Unit - UG1485

Versal Architecture Premium Series Libraries Guide (UG1485)
Document ID
UG1485
Release Date
2025-09-17
Version
2025.1 English

Parameterized Macro: AXI Streaming (AXI Full) NOC Master Unit

  • MACRO_GROUP: XPM
  • MACRO_SUBGROUP: NOC

Introduction

This macro is used to instantiate AXI Streaming (AXI Full) NOC Master Unit.

Port Descriptions

Port Direction Width Domain Sense Handling if Unused Function
dst_id_err Output 1 s_axis_aclk LEVEL_HIGH Active Indicates DST ID error
s_axis_aclk Input 1 NA EDGE_RISING Active Slave Interface Clock: All signals on slave interface are sampled on the rising edge of this clock.
s_axis_tdata Input DATA_WIDTH s_axis_aclk NA Active TDATA: The primary payload that is used to provide the data that is passing across the interface. The width of the data payload is an integer number of bytes.
s_axis_tdest Input DST_ID_WIDTH s_axis_aclk NA Active TDEST: Provides routing information for the data stream.
s_axis_tid Input ID_WIDTH s_axis_aclk NA Active TID: Identification tag for the data transfer
s_axis_tkeep Input DATA_WIDTH / 8 s_axis_aclk NA Active TKEEP: is the byte qualifier that indicates whether content of the associated byte of TDATA is processed as part of the data stream.
s_axis_tlast Input 1 s_axis_aclk LEVEL_HIGH Active TLAST: Indicates the boundary of a packet.
s_axis_tready Output 1 s_axis_aclk LEVEL_HIGH Active TREADY: Indicates that the receiver can accept a transfer in the current cycle.
s_axis_tvalid Input 1 s_axis_aclk LEVEL_HIGH Active TVALID: indicates the Transmitter is driving a valid transfer. A transfer takes place when both TVALID and TREADY are asserted.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
DATA_WIDTH DECIMAL 512, 128, 256 512 Defines the width of the DATA ports, s_axi_rdata, s_axi_wdata.
DST_ID_WIDTH DECIMAL 0 to 12 4 Defines the width of the TDEST port
ID_WIDTH DECIMAL 0 to 16 16 Defines the width of the ID ports, TID
NOC_FABRIC STRING "VNOC", "BLI", "pl", "pl_hbm" "VNOC"
  • "VNOC"/"pl" - Choosing the VNOC NMU of given device
  • "BLI"/"pl_hbm" - Disables Packet FIFO mode

VHDL Instantiation Template


-- xpm_nmu_strm: AXI Streaming (AXI Full) NOC Master Unit
-- Xilinx Parameterized Macro, version 2025.1

xpm_nmu_strm_inst : xpm_nmu_strm
generic map (
   DATA_WIDTH => 512,    -- DECIMAL
   DST_ID_WIDTH => 4,    -- DECIMAL
   ID_WIDTH => 16,       -- DECIMAL
   NOC_FABRIC => "VNOC"  -- STRING
)
port map (
   dst_id_err => dst_id_err,       -- 1-bit output: Indicates DST ID error
   s_axis_tready => s_axis_tready, -- 1-bit output: TREADY: Indicates that the receiver can accept a transfer in the current cycle.
   s_axis_aclk => s_axis_aclk,     -- 1-bit input: Slave Interface Clock: All signals on slave interface are sampled on the rising edge of this
                                   -- clock.

   s_axis_tdata => s_axis_tdata,   -- DATA_WIDTH-bit input: TDATA: The primary payload that is used to provide the data that is passing across the
                                   -- interface. The width of the data payload is an integer number of bytes.

   s_axis_tdest => s_axis_tdest,   -- DST_ID_WIDTH-bit input: TDEST: Provides routing information for the data stream.
   s_axis_tid => s_axis_tid,       -- ID_WIDTH-bit input: TID: Identification tag for the data transfer
   s_axis_tkeep => s_axis_tkeep,   -- DATA_WIDTH/8-bit input: TKEEP: is the byte qualifier that indicates whether content of the associated byte
                                   -- of TDATA is processed as part of the data stream.

   s_axis_tlast => s_axis_tlast,   -- 1-bit input: TLAST: Indicates the boundary of a packet.
   s_axis_tvalid => s_axis_tvalid  -- 1-bit input: TVALID: indicates the Transmitter is driving a valid transfer. A transfer takes place when both
                                   -- TVALID and TREADY are asserted.

);

-- End of xpm_nmu_strm_inst instantiation

Verilog Instantiation Template


// xpm_nmu_strm: AXI Streaming (AXI Full) NOC Master Unit
// Xilinx Parameterized Macro, version 2025.1

xpm_nmu_strm #(
   .DATA_WIDTH(512),    // DECIMAL
   .DST_ID_WIDTH(4),    // DECIMAL
   .ID_WIDTH(16),       // DECIMAL
   .NOC_FABRIC("VNOC")  // STRING
)
xpm_nmu_strm_inst (
   .dst_id_err(dst_id_err),       // 1-bit output: Indicates DST ID error
   .s_axis_tready(s_axis_tready), // 1-bit output: TREADY: Indicates that the receiver can accept a transfer in the current cycle.
   .s_axis_aclk(s_axis_aclk),     // 1-bit input: Slave Interface Clock: All signals on slave interface are sampled on the rising edge of this
                                  // clock.

   .s_axis_tdata(s_axis_tdata),   // DATA_WIDTH-bit input: TDATA: The primary payload that is used to provide the data that is passing across the
                                  // interface. The width of the data payload is an integer number of bytes.

   .s_axis_tdest(s_axis_tdest),   // DST_ID_WIDTH-bit input: TDEST: Provides routing information for the data stream.
   .s_axis_tid(s_axis_tid),       // ID_WIDTH-bit input: TID: Identification tag for the data transfer
   .s_axis_tkeep(s_axis_tkeep),   // DATA_WIDTH/8-bit input: TKEEP: is the byte qualifier that indicates whether content of the associated byte of
                                  // TDATA is processed as part of the data stream.

   .s_axis_tlast(s_axis_tlast),   // 1-bit input: TLAST: Indicates the boundary of a packet.
   .s_axis_tvalid(s_axis_tvalid)  // 1-bit input: TVALID: indicates the Transmitter is driving a valid transfer. A transfer takes place when both
                                  // TVALID and TREADY are asserted.

);

// End of xpm_nmu_strm_inst instantiation