XPM_FIFO_AXIS_SV - 2025.2 English - Parameterized Macro: AXI Memory Mapped (AXI Stream) FIFO - UG1485

System Verilog Instantiation Template

// xpm_fifo_axis_sv 	: In order to incorporate this function into the design,
//   System Verilog     : the following instance declaration needs to be placed
//   instance    		: in the body of the design code.  The instance name
//  declaration  		: (xpm_fifo_axis_sv_inst) and/or the port declarations within the
//     code      		: parenthesis may be changed to properly reference and
//               		: connect this function to the design.  All inputs
//               		: and outputs must be connected.

// -------------- Begin Cut here for INTERFACE Include ------- // INCLUDE_TAG
`include "vivado_interfaces.svh" 
// -- INCLUDE_TAG_END ------ End INTERFACE Include ------------

// -------------- Begin Cut here for INTERFACE Template ------- // INTF_TAG 
// Default parameter used by the module are for S_AXI
vivado_axis_v1_0 #(
    .TDATA_NUM_BYTES(1),
    .TDEST_WIDTH(4),
    .TID_WIDTH(6)
) S_AXIS();

//  -- INTF_TAG_END -------------- End INTERFACE Template ------------------ 

//  <-----Cut code below this line---->
// xpm_fifo_axis_sv: AXI Stream FIFO
// Xilinx Parameterized Macro, version 2025.2

xpm_fifo_axis_sv #(
    .TDATA_WIDTH(TDATA_NUM_BYTES*8),     // DECIMAL
    .TDEST_WIDTH(TDEST_WIDTH),            // DECIMAL
    .TID_WIDTH(TID_WIDTH),                // DECIMAL
    .TUSER_WIDTH(1),                      // DECIMAL
    .CASCADE_HEIGHT(0),                   // DECIMAL
    .CDC_SYNC_STAGES(2),                  // DECIMAL
    .CLOCKING_MODE("common_clock"),      // String
    .ECC_MODE("no_ecc"),                  // String
    .EN_SIM_ASSERT_ERR("warning"),       // String
    .FIFO_DEPTH(2048),                   // DECIMAL
    .FIFO_MEMORY_TYPE("auto"),           // String
    .PACKET_FIFO("false"),               // String
    .PROG_EMPTY_THRESH(10),              // DECIMAL
    .PROG_FULL_THRESH(10),               // DECIMAL
    .RD_DATA_COUNT_WIDTH(1),             // DECIMAL
    .RELATED_CLOCKS(0),                  // DECIMAL
    .SIM_ASSERT_CHK(0),                  // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
    .USE_ADV_FEATURES("1000"),           // String
    .WR_DATA_COUNT_WIDTH(1)              // DECIMAL
)
xpm_fifo_axis_sv_inst (
    .almost_empty_axis(almost_empty_axis),   // 1-bit output: Almost Empty : When asserted, this signal indicates that only one more read can be
                                             // performed before the FIFO goes to empty.

    .almost_full_axis(almost_full_axis),     // 1-bit output: Almost Full: When asserted, this signal indicates that only one more write can be
                                             // performed before the FIFO is full.

    .dbiterr_axis(dbiterr_axis),             // 1-bit output: Double Bit Error- Indicates that the ECC decoder detected a double-bit error and data
                                             // in the FIFO core is corrupted.

    .S_AXIS (S_AXIS.slave),

    .M_AXIS (M_AXIS.master),

    .prog_empty_axis(prog_empty_axis),       // 1-bit output: Programmable Empty- This signal is asserted when the number of words in the FIFO is
                                             // less than or equal to the programmable empty threshold value. It is de-asserted when the number of
                                             // words in the FIFO exceeds the programmable empty threshold value.

    .prog_full_axis(prog_full_axis),         // 1-bit output: Programmable Full: This signal is asserted when the number of words in the FIFO is
                                             // greater than or equal to the programmable full threshold value. It is de-asserted when the number
                                             // of words in the FIFO is less than the programmable full threshold value.

    .rd_data_count_axis(rd_data_count_axis), // RD_DATA_COUNT_WIDTH-bit output: Read Data Count- This bus indicates the number of words available
                                             // for reading in the FIFO.

    .sbiterr_axis(sbiterr_axis),             // 1-bit output: Single Bit Error- Indicates that the ECC decoder detected and fixed a single-bit
                                             // error.

    .wr_data_count_axis(wr_data_count_axis), // WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates the number of words written
                                             // into the FIFO.

    .injectdbiterr_axis(injectdbiterr_axis), // 1-bit input: Double Bit Error Injection- Injects a double bit error if the ECC feature is used.

    .injectsbiterr_axis(injectsbiterr_axis), // 1-bit input: Single Bit Error Injection- Injects a single bit error if the ECC feature is used.

    .m_aclk(m_aclk),                         // 1-bit input: Master Interface Clock: All signals on master interface are sampled on the rising edge
                                             // of this clock.

    .s_aclk(s_aclk),                         // 1-bit input: Slave Interface Clock: All signals on slave interface are sampled on the rising edge
                                             // of this clock.

    .s_aresetn(s_aresetn)                    // 1-bit input: Active low asynchronous reset.
);

// End of xpm_fifo_axis_sv_inst instantiation