XPM_FIFO_AXIS - 2025.2 English - Parameterized Macro: AXI Stream FIFO

MACRO_GROUP: XPM
MACRO_SUBGROUP: XPM_FIFO

Introduction

This macro is used to instantiate AXI Stream FIFO.

AXI Stream FIFO is derived from the XPM_FIFO_SYNC and XPM_FIFO_ASYNC. The AXI Stream protocol uses a two-way valid and ready handshake mechanism. The information source uses the valid signal to show when valid data or control information is available on the channel. The information destination uses the ready signal to show when it can accept the data.

Timing Diagrams

Figure 1. Timing for Read and Write Operations to the AXI Stream FIFO

In the timing diagram above, the information source generates a valid signal to indicate when data is available. The destination generates a ready signal to indicate that it can accept data, and transfer occurs only when both the valid and ready signals are High.

Because the AXI Stream FIFO is derived from XPM_FIFO_SYNC and XPM_FIFO_ASYNC, much of the behavior is common between them. The ready signal is generated based on availability of space in the FIFO and is held high to allow writes to the FIFO. The ready signal is pulled Low only when there is no space in the FIFO left to perform additional writes. The valid signal is generated based on availability of data in the FIFO and is held High to allow reads to be performed from the FIFO. The valid signal is pulled Low only when there is no data available to be read from the FIFO. The information signals are mapped to the din and dout bus of Native interface FIFOs. The width of the AXI FIFO is determined by concatenating all of the information signals of the AXI interface. The information signals include all AXI signals except for the valid and ready handshake signals.

The AXI Stream FIFO operates only in First-Word Fall-Through mode. The First-Word Fall-Through (FWFT) feature provides the ability to look ahead to the next word available from the FIFO without issuing a read operation. When data is available in the FIFO, the first word falls through the FIFO and appears automatically on the output data bus.

Port Descriptions

Port	Direction	Width	Domain	Sense	Handling if Unused	Function
almost_empty_axis	Output	1	m_aclk	LEVEL_HIGH	DoNotCare	Almost Empty : When asserted, this signal indicates that only one more read can be performed before the FIFO goes to empty.
almost_full_axis	Output	1	s_aclk	LEVEL_HIGH	DoNotCare	Almost Full: When asserted, this signal indicates that only one more write can be performed before the FIFO is full.
dbiterr_axis	Output	1	m_aclk	LEVEL_HIGH	DoNotCare	Double Bit Error- Indicates that the ECC decoder detected a double-bit error and data in the FIFO core is corrupted.
injectdbiterr_axis	Input	1	s_aclk	LEVEL_HIGH	0	Double Bit Error Injection- Injects a double bit error if the ECC feature is used.
injectsbiterr_axis	Input	1	s_aclk	LEVEL_HIGH	0	Single Bit Error Injection- Injects a single bit error if the ECC feature is used.
m_aclk	Input	1	NA	EDGE_RISING	Active	Master Interface Clock: All signals on master interface are sampled on the rising edge of this clock.
m_axis_tdata	Output	TDATA_WIDTH	m_aclk	NA	Active	TDATA: The primary payload that is used to provide the data that is passing across the interface. The width of the data payload is an integer number of bytes.
m_axis_tdest	Output	TDEST_WIDTH	m_aclk	NA	Active	TDEST: Provides routing information for the data stream.
m_axis_tid	Output	TID_WIDTH	m_aclk	NA	Active	TID: The data stream identifier that indicates different streams of data.
m_axis_tkeep	Output	TDATA_WIDTH / 8	m_aclk	NA	Active	TKEEP: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed as part of the data stream. Associated bytes that have the TKEEP byte qualifier deasserted are null bytes and can be removed from the data stream. For a 64-bit DATA, bit 0 corresponds to the least significant byte on DATA, and bit 7 corresponds to the most significant byte. For example: KEEP[0] = 1b, DATA[7:0] is not a NULL byte KEEP[7] = 0b, DATA[63:56] is a NULL byte
m_axis_tlast	Output	1	m_aclk	LEVEL_HIGH	Active	TLAST: Indicates the boundary of a packet.
m_axis_tready	Input	1	m_aclk	LEVEL_HIGH	Active	TREADY: Indicates that the slave can accept a transfer in the current cycle.
m_axis_tstrb	Output	TDATA_WIDTH / 8	m_aclk	NA	Active	TSTRB: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte. For a 64-bit DATA, bit 0 corresponds to the least significant byte on DATA, and bit 0 corresponds to the least significant byte on DATA, and bit 7 corresponds to the most significant byte. For example: STROBE[0] = 1b, DATA[7:0] is valid STROBE[7] = 0b, DATA[63:56] is not valid
m_axis_tuser	Output	TUSER_WIDTH	m_aclk	NA	Active	TUSER: The user-defined sideband information that can be transmitted alongside the data stream.
m_axis_tvalid	Output	1	m_aclk	LEVEL_HIGH	Active	TVALID: Indicates that the master is driving a valid transfer. A transfer takes place when both TVALID and TREADY are asserted
prog_empty_axis	Output	1	m_aclk	LEVEL_HIGH	DoNotCare	Programmable Empty- This signal is asserted when the number of words in the FIFO is less than or equal to the programmable empty threshold value. It is de-asserted when the number of words in the FIFO exceeds the programmable empty threshold value.
prog_full_axis	Output	1	s_aclk	LEVEL_HIGH	DoNotCare	Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal to the programmable full threshold value. It is de-asserted when the number of words in the FIFO is less than the programmable full threshold value.
rd_data_count_axis	Output	RD_DATA_COUNT_WIDTH	m_aclk	NA	DoNotCare	Read Data Count- This bus indicates the number of words available for reading in the FIFO.
s_aclk	Input	1	NA	EDGE_RISING	Active	Slave Interface Clock: All signals on slave interface are sampled on the rising edge of this clock.
s_aresetn	Input	1	NA	LEVEL_LOW	Active	Active low asynchronous reset.
s_axis_tdata	Input	TDATA_WIDTH	s_aclk	NA	Active	TDATA: The primary payload that is used to provide the data that is passing across the interface. The width of the data payload is an integer number of bytes.
s_axis_tdest	Input	TDEST_WIDTH	s_aclk	NA	Active	TDEST: Provides routing information for the data stream.
s_axis_tid	Input	TID_WIDTH	s_aclk	NA	Active	TID: The data stream identifier that indicates different streams of data.
s_axis_tkeep	Input	TDATA_WIDTH / 8	s_aclk	NA	Active	TKEEP: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed as part of the data stream. Associated bytes that have the TKEEP byte qualifier deasserted are null bytes and can be removed from the data stream. For a 64-bit DATA, bit 0 corresponds to the least significant byte on DATA, and bit 7 corresponds to the most significant byte. For example: KEEP[0] = 1b, DATA[7:0] is not a NULL byte KEEP[7] = 0b, DATA[63:56] is a NULL byte
s_axis_tlast	Input	1	s_aclk	LEVEL_HIGH	Active	TLAST: Indicates the boundary of a packet.
s_axis_tready	Output	1	s_aclk	LEVEL_HIGH	Active	TREADY: Indicates that the slave can accept a transfer in the current cycle.
s_axis_tstrb	Input	TDATA_WIDTH / 8	s_aclk	NA	Active	TSTRB: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte. For a 64-bit DATA, bit 0 corresponds to the least significant byte on DATA, and bit 0 corresponds to the least significant byte on DATA, and bit 7 corresponds to the most significant byte. For example: STROBE[0] = 1b, DATA[7:0] is valid STROBE[7] = 0b, DATA[63:56] is not valid
s_axis_tuser	Input	TUSER_WIDTH	s_aclk	NA	Active	TUSER: The user-defined sideband information that can be transmitted alongside the data stream.
s_axis_tvalid	Input	1	s_aclk	LEVEL_HIGH	Active	TVALID: Indicates that the master is driving a valid transfer. A transfer takes place when both TVALID and TREADY are asserted
sbiterr_axis	Output	1	m_aclk	LEVEL_HIGH	DoNotCare	Single Bit Error- Indicates that the ECC decoder detected and fixed a single-bit error.
wr_data_count_axis	Output	WR_DATA_COUNT_WIDTH	s_aclk	NA	DoNotCare	Write Data Count: This bus indicates the number of words written into the FIFO.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
CASCADE_HEIGHT	DECIMAL	0 to 64	0	0- No Cascade Height, Allow Vivado Synthesis to choose. 1 or more - Vivado Synthesis sets the specified value as Cascade Height.
CDC_SYNC_STAGES	DECIMAL	2 to 8	2	Specifies the number of synchronization stages on the CDC path. Applicable only if CLOCKING_MODE = "independent_clock"
CLOCKING_MODE	STRING	"common_clock", "independent_clock"	"common_clock"	Designate whether AXI Stream FIFO is clocked with a common clock or with independent clocks- "common_clock"- Common clocking; clock both write and read domain s_aclk "independent_clock"- Independent clocking; clock write domain with s_aclk and read domain with m_aclk
ECC_MODE	STRING	"no_ecc", "en_ecc"	"no_ecc"	"no_ecc" - Disables ECC "en_ecc" - Enables both ECC Encoder and Decoder NOTE: ECC_MODE should be "no_ecc" if FIFO_MEMORY_TYPE is set to "auto". Violating this may result incorrect behavior.
EN_SIM_ASSERT_ERR	STRING	String	"warning"	"warning" - Report warning message for FIFO overflow and underflow in simulation. "error" - Report error message for FIFO overflow and underflow in simulation. "fatal" - Report fatal message for FIFO overflow and underflow in simulation.
FIFO_DEPTH	DECIMAL	16 to 4194304	2048	Defines the AXI Stream FIFO Write Depth, must be power of two NOTE: The maximum FIFO size (width x depth) is limited to 150-Megabits.
FIFO_MEMORY_TYPE	STRING	"auto", "block", "distributed", "ultra"	"auto"	Designate the fifo memory primitive (resource type) to use- "auto"- Allow Vivado Synthesis to choose "block"- Block RAM FIFO "distributed"- Distributed RAM FIFO "ultra"- URAM FIFO NOTE: There may be a behavior mismatch if Block RAM or Ultra RAM specific features, like ECC or Asymmetry, are selected with FIFO_MEMORY_TYPE set to "auto".
PACKET_FIFO	STRING	"false", "true"	"false"	"true"- Enables Packet FIFO mode "false"- Disables Packet FIFO mode
PROG_EMPTY_THRESH	DECIMAL	5 to 4194301	10	Specifies the minimum number of read words in the FIFO at or below which prog_empty is asserted. Min_Value = 5 Max_Value = FIFO_WRITE_DEPTH - 5 NOTE: The default threshold value is dependent on default FIFO_WRITE_DEPTH value. If FIFO_WRITE_DEPTH value is changed, ensure the threshold value is within the valid range though the programmable flags are not used.
PROG_FULL_THRESH	DECIMAL	5 to 4194301	10	Specifies the maximum number of write words in the FIFO at or above which prog_full is asserted. Min_Value = 5 + CDC_SYNC_STAGES Max_Value = FIFO_WRITE_DEPTH - 5 NOTE: The default threshold value is dependent on default FIFO_WRITE_DEPTH value. If FIFO_WRITE_DEPTH value is changed, ensure the threshold value is within the valid range though the programmable flags are not used.
RD_DATA_COUNT_WIDTH	DECIMAL	1 to 23	1	Specifies the width of rd_data_count_axis. To reflect the correct value, the width should be log2(FIFO_DEPTH)+1.
RELATED_CLOCKS	DECIMAL	0 to 1	0	Specifies if the s_aclk and m_aclk are related having the same source but different clock ratios. Applicable only if CLOCKING_MODE = "independent_clock"
SIM_ASSERT_CHK	DECIMAL	0 to 1	0	0- Disable simulation message reporting. Messages related to potential misuse will not be reported. 1- Enable simulation message reporting. Messages related to potential misuse will be reported.
TDATA_WIDTH	DECIMAL	8 to 2048	32	Defines the width of the TDATA port, s_axis_tdata and m_axis_tdata NOTE: The maximum FIFO size (width x depth) is limited to 150-Megabits.
TDEST_WIDTH	DECIMAL	1 to 32	1	Defines the width of the TDEST port, s_axis_tdest and m_axis_tdest
TID_WIDTH	DECIMAL	1 to 32	1	Defines the width of the ID port, s_axis_tid and m_axis_tid
TUSER_WIDTH	DECIMAL	1 to 4086	1	Defines the width of the TUSER port, s_axis_tuser and m_axis_tuser
USE_ADV_FEATURES	STRING	String	"1000"	Enables almost_empty_axis, rd_data_count_axis, prog_empty_axis, almost_full_axis, wr_data_count_axis, prog_full_axis sideband signals. Setting USE_ADV_FEATURES[1] to 1 enables prog_full flag; Default value of this bit is 0 Setting USE_ADV_FEATURES[2] to 1 enables wr_data_count; Default value of this bit is 0 Setting USE_ADV_FEATURES[3] to 1 enables almost_full flag; Default value of this bit is 0 Setting USE_ADV_FEATURES[9] to 1 enables prog_empty flag; Default value of this bit is 0 Setting USE_ADV_FEATURES[10] to 1 enables rd_data_count; Default value of this bit is 0 Setting USE_ADV_FEATURES[11] to 1 enables almost_empty flag; Default value of this bit is 0
WR_DATA_COUNT_WIDTH	DECIMAL	1 to 23	1	Specifies the width of wr_data_count_axis. To reflect the correct value, the width should be log2(FIFO_DEPTH)+1.

XPM_FIFO_AXIS - 2025.2 English - Parameterized Macro: AXI Stream FIFO - UG1485

Versal Architecture Premium Series Libraries Guide (UG1485)

Introduction

Timing Diagrams

Port Descriptions

Design Entry Method

Available Attributes

VHDL Instantiation Template

Verilog Instantiation Template

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