XPM_FIFO_AXIF_SV - 2025.2 English - Parameterized Macro: AXI Memory Mapped (AXI Full) FIFO - UG1485

System Verilog Instantiation Template

// xpm_fifo_axif_sv : In order to incorporate this function into the design,
//   System Verilog : the following instance declaration needs to be placed
//   instance       : in the body of the design code.  The instance name
//  declaration     : (xpm_fifo_axif_sv_inst) and/or the port declarations within the
//     code         : parenthesis may be changed to properly reference and
//                  : connect this function to the design.  All inputs
//                  : and outputs must be connected.
//  Please reference the appropriate libraries guide for additional information on the XPM modules.

// -------------- Begin Cut here for INTERFACE Include ------- // INCLUDE_TAG
`include "vivado_interfaces.svh" 
// -- INCLUDE_TAG_END ------ End INTERFACE Include ------------

// -------------- Begin Cut here for INTERFACE Template ------- // INTF_TAG 
// Default parameter used by the module are for S_AXI
vivado_aximm_v1_0 #(
    .ID_WIDTH(1),
    .ADDR_WIDTH(32),
    .AWUSER_WIDTH(16),
    .DATA_WIDTH(32),
    .WUSER_WIDTH(4),
    .BUSER_WIDTH(16),
    .ARUSER_WIDTH(16),
    .RUSER_WIDTH(4)
) S_AXI(), M_AXI();

//  -- INTF_TAG_END -------------- End INTERFACE Template ------------------ 

//  <-----Cut code below this line---->
// xpm_fifo_axif_sv: AXI Memory Mapped (AXI Full) FIFO
// Xilinx Parameterized Macro, version 2025.2

xpm_fifo_axif_sv #(
    .AXI_ADDR_WIDTH(ADDR_WIDTH),               // DECIMAL
    .AXI_ARUSER_WIDTH(ARUSER_WIDTH),           // DECIMAL
    .AXI_AWUSER_WIDTH(AWUSER_WIDTH),           // DECIMAL
    .AXI_BUSER_WIDTH(BUSER_WIDTH),             // DECIMAL
    .AXI_DATA_WIDTH(DATA_WIDTH),               // DECIMAL
    .AXI_ID_WIDTH(ID_WIDTH),                   // DECIMAL
    .AXI_RUSER_WIDTH(RUSER_WIDTH),             // DECIMAL
    .AXI_WUSER_WIDTH(WUSER_WIDTH),             // DECIMAL
    .CASCADE_HEIGHT(0),                         // DECIMAL
    .CDC_SYNC_STAGES(2),                        // DECIMAL
    .CLOCKING_MODE("common_clock"),            // String
    .ECC_MODE_RDCH("no_ecc"),                  // String
    .ECC_MODE_WDCH("no_ecc"),                  // String
    .EN_RESET_SYNCHRONIZER(1),                 // DECIMAL; 0=disable synchronizer in the reset path, 1=enable synchronizer in the reset path
    .EN_SIM_ASSERT_ERR("warning"),             // String
    .FIFO_DEPTH_RACH(2048),                     // DECIMAL
    .FIFO_DEPTH_RDCH(2048),                     // DECIMAL
    .FIFO_DEPTH_WACH(2048),                     // DECIMAL
    .FIFO_DEPTH_WDCH(2048),                     // DECIMAL
    .FIFO_DEPTH_WRCH(2048),                     // DECIMAL
    .FIFO_MEMORY_TYPE_RACH("auto"),             // String
    .FIFO_MEMORY_TYPE_RDCH("auto"),             // String
    .FIFO_MEMORY_TYPE_WACH("auto"),             // String
    .FIFO_MEMORY_TYPE_WDCH("auto"),             // String
    .FIFO_MEMORY_TYPE_WRCH("auto"),             // String
    .PACKET_FIFO("false"),                       // String
    .PROG_EMPTY_THRESH_RDCH(10),                 // DECIMAL
    .PROG_EMPTY_THRESH_WDCH(10),                 // DECIMAL
    .PROG_FULL_THRESH_RDCH(10),                  // DECIMAL
    .PROG_FULL_THRESH_WDCH(10),                  // DECIMAL
    .RD_DATA_COUNT_WIDTH_RDCH(1),                // DECIMAL
    .RD_DATA_COUNT_WIDTH_WDCH(1),                // DECIMAL
    .SIM_ASSERT_CHK(0),                          // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
    .USE_ADV_FEATURES_RDCH("1000"),              // String
    .USE_ADV_FEATURES_WDCH("1000"),              // String
    .WR_DATA_COUNT_WIDTH_RDCH(1),                // DECIMAL
    .WR_DATA_COUNT_WIDTH_WDCH(1)                  // DECIMAL
)
xpm_fifo_axif_sv_inst (
    .M_AXI(M_AXI.master),

    .S_AXI(S_AXI.slave),

    .dbiterr_rdch(dbiterr_rdch),             // 1-bit output: Double Bit Error- Indicates that the ECC decoder detected a double-bit error and data
                                             // in the FIFO core is corrupted.

    .dbiterr_wdch(dbiterr_wdch),             // 1-bit output: Double Bit Error- Indicates that the ECC decoder detected a double-bit error and data
                                             // in the FIFO core is corrupted.

    .prog_empty_rdch(prog_empty_rdch),       // 1-bit output: Programmable Empty- This signal is asserted when the number of words in the Read Data
                                             // Channel FIFO is less than or equal to the programmable empty threshold value. It is de-asserted
                                             // when the number of words in the Read Data Channel FIFO exceeds the programmable empty threshold
                                             // value.

    .prog_empty_wdch(prog_empty_wdch),       // 1-bit output: Programmable Empty- This signal is asserted when the number of words in the Write
                                             // Data Channel FIFO is less than or equal to the programmable empty threshold value. It is
                                             // de-asserted when the number of words in the Write Data Channel FIFO exceeds the programmable empty
                                             // threshold value.

    .prog_full_rdch(prog_full_rdch),         // 1-bit output: Programmable Full: This signal is asserted when the number of words in the Read Data
                                             // Channel FIFO is greater than or equal to the programmable full threshold value. It is de-asserted
                                             // when the number of words in the Read Data Channel FIFO is less than the programmable full threshold
                                             // value.

    .prog_full_wdch(prog_full_wdch),         // 1-bit output: Programmable Full: This signal is asserted when the number of words in the Write Data
                                             // Channel FIFO is greater than or equal to the programmable full threshold value. It is de-asserted
                                             // when the number of words in the Write Data Channel FIFO is less than the programmable full
                                             // threshold value.

    .rd_data_count_rdch(rd_data_count_rdch), // RD_DATA_COUNT_WIDTH_RDCH-bit output: Read Data Count- This bus indicates the number of words
                                             // available for reading in the Read Data Channel FIFO.

    .rd_data_count_wdch(rd_data_count_wdch), // RD_DATA_COUNT_WIDTH_WDCH-bit output: Read Data Count- This bus indicates the number of words
                                             // available for reading in the Write Data Channel FIFO.

    .sbiterr_rdch(sbiterr_rdch),             // 1-bit output: Single Bit Error- Indicates that the ECC decoder detected and fixed a single-bit
                                             // error.

    .sbiterr_wdch(sbiterr_wdch),             // 1-bit output: Single Bit Error- Indicates that the ECC decoder detected and fixed a single-bit
                                             // error.

    .wr_data_count_rdch(wr_data_count_rdch), // WR_DATA_COUNT_WIDTH_RDCH-bit output: Write Data Count: This bus indicates the number of words
                                             // written into the Read Data Channel FIFO.

    .wr_data_count_wdch(wr_data_count_wdch), // WR_DATA_COUNT_WIDTH_WDCH-bit output: Write Data Count: This bus indicates the number of words
                                             // written into the Write Data Channel FIFO.

    .injectdbiterr_rdch(injectdbiterr_rdch), // 1-bit input: Double Bit Error Injection- Injects a double bit error if the ECC feature is used.

    .injectdbiterr_wdch(injectdbiterr_wdch), // 1-bit input: Double Bit Error Injection- Injects a double bit error if the ECC feature is used.

    .injectsbiterr_rdch(injectsbiterr_rdch), // 1-bit input: Single Bit Error Injection- Injects a single bit error if the ECC feature is used.

    .injectsbiterr_wdch(injectsbiterr_wdch), // 1-bit input: Single Bit Error Injection- Injects a single bit error if the ECC feature is used.

    .m_aclk(clk),                            // 1-bit input: Master Interface Clock: All signals on master interface are sampled on the rising edge
                                             // of this clock.

    .s_aclk(clk),                            // 1-bit input: Slave Interface Clock: All signals on slave interface are sampled on the rising edge
                                             // of this clock.

    .s_aresetn(reset_n)                      // 1-bit input: Active low asynchronous reset.
);

// End of xpm_fifo_axif_sv_inst instantiation