Parameterized Macro: Asynchronous Reset Synchronizer
- MACRO_GROUP: XPM
- MACRO_SUBGROUP: XPM_CDC
Introduction
This macro synchronizes an asynchronous reset signal to the destination clock domain. The resulting reset output always asserts asynchronously in relation to the input, but the output always deasserts synchronous to the destination clock domain.
You define the reset-signal polarity and the macro's minimum asserted output pulse width. The number of register stages in the synchronizers determines that minimum output pulse width.
Port Descriptions
| Port | Direction | Width | Domain | Sense | Handling if Unused | Function |
|---|---|---|---|---|---|---|
| dest_arst | Output | 1 | dest_clk | NA | Active |
This registered output synchronizes the src_arst asynchronous reset signal to the destination clock domain. NOTE: This signal asserts asynchronously but deasserts synchronously to dest_clk. The width of the reset signal is at least (DEST_SYNC_FF*dest_clk) period. |
| dest_clk | Input | 1 | NA | EDGE_RISING | Active | Destination clock. |
| src_arst | Input | 1 | NA | NA | Active | Source asynchronous reset signal. |
Design Entry Method
| Instantiation | Yes |
| Inference | No |
| IP and IP Integrator Catalog | No |
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| DEST_SYNC_FF | DECIMAL | 2 to 10 | 4 | Number of register stages to synchronize the signal in the destination clock domain. This parameter also determines the minimum width of the asserted reset signal. |
| INIT_SYNC_FF | DECIMAL | 0, 1 | 0 |
0: Disable behavioral simulation initialization values on synchronization registers. 1: Enable behavioral simulation initialization values on synchronization registers. |
| RST_ACTIVE_HIGH | DECIMAL | 0, 1 | 0 |
Defines the polarity of the asynchronous reset signal.
|
VHDL Instantiation Template
Library xpm;
use xpm.vcomponents.all;
-- xpm_cdc_async_rst: Asynchronous Reset Synchronizer
-- Xilinx Parameterized Macro, version 2026.1
xpm_cdc_async_rst_inst : xpm_cdc_async_rst
generic map (
DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
RST_ACTIVE_HIGH => 0 -- DECIMAL; 0=active-Low reset, 1=active-High reset
)
port map (
src_arst => src_arst, -- 1-bit input: Source asynchronous reset signal.
dest_clk => dest_clk, -- 1-bit input: Destination clock.
dest_arst => dest_arst -- 1-bit output: This registered output synchronizes the src_arst asynchronous reset signal to the destination clock
-- domain. NOTE: This signal asserts asynchronously but deasserts synchronously to dest_clk. The width of the reset
-- signal is at least (DEST_SYNC_FF*dest_clk) period.
);
-- End of xpm_cdc_async_rst_inst instantiation
Verilog Instantiation Template
// xpm_cdc_async_rst: Asynchronous Reset Synchronizer
// Xilinx Parameterized Macro, version 2026.1
xpm_cdc_async_rst #(
.DEST_SYNC_FF(4), // DECIMAL; range: 2-10
.INIT_SYNC_FF(0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.RST_ACTIVE_HIGH(0) // DECIMAL; 0=active-Low reset, 1=active-High reset
)
xpm_cdc_async_rst_inst (
.src_arst(src_arst), // 1-bit input: Source asynchronous reset signal.
.dest_clk(dest_clk), // 1-bit input: Destination clock.
.dest_arst(dest_arst) // 1-bit output: This registered output synchronizes the src_arst asynchronous reset signal to the destination clock
// domain. NOTE: This signal asserts asynchronously but deasserts synchronously to dest_clk. The width of the reset
// signal is at least (DEST_SYNC_FF*dest_clk) period.
);
// End of xpm_cdc_async_rst_inst instantiation
Related Information
- XPM CDC Testbench File (xpm-cdc-testbench.zip)