RAM64M8 - 2024.1 English

Versal Architecture Premium Series Libraries Guide (UG1485)

Document ID
UG1485
Release Date
2024-05-30
Version
2024.1 English

Primitive: 64-Deep by 8-bit Wide Multi Port Random Access Memory (Select RAM)

  • PRIMITIVE_GROUP: CLB
  • PRIMITIVE_SUBGROUP: LUTRAM

Introduction

This design element is a 64-bit deep by 8-bit wide, multi-port, random access memory with synchronous write and asynchronous independent bit wide read capability. This RAM is implemented using the LUT resources of the device (also known as SelectRAM™+) and does not consume any of the block RAM resources of the device. This component is implemented in a single CLB and consists of one 8-bit write, 1-bit read port, and seven separate 1-bit read ports from the same memory allowing for byte-wide write and independent bit read access RAM.
  • If the 7 inputs are all tied to the same data inputs, the RAM can become a 1 read/write port, 7 independent read port 64x1 octal port memory.

  • If DIH is grounded, DOH is not used.

  • If ADDRA through ADDRG are tied to the same address, the RAM becomes a 64x14 simple dual port RAM.

  • If ADDRA through ADDRH are tied together, the RAM becomes a 64x16 single port RAM.

There are several other possible configurations for this RAM.

Port Descriptions

Port Direction Width Function
DOA Output 1 Read port data outputs addressed by ADDRA
DOB Output 1 Read port data outputs addressed by ADDRB
DOC Output 1 Read port data outputs addressed by ADDRC
DOD Output 1 Read port data outputs addressed by ADDRD
DOE Output 1 Read port data outputs addressed by ADDRE
DOF Output 1 Read port data outputs addressed by ADDRF
DOG Output 1 Read port data outputs addressed by ADDRG
DOH Output 1 Read/Write port data outputs addressed by ADDRH
DIA Input 1 Data write input addressed by ADDRH (read output is addressed by ADDRA)
DIB Input 1 Data write input addressed by ADDRH (read output is addressed by ADDRB)
DIC Input 1 Data write input addressed by ADDRH (read output is addressed by ADDRC)
DID Input 1 Data write input addressed by ADDRH (read output is addressed by ADDRD)
DIE Input 1 Data write input addressed by ADDRH (read output is addressed by ADDRE)
DIF Input 1 Data write input addressed by ADDRH (read output is addressed by ADDRF)
DIG Input 1 Data write input addressed by ADDRH (read output is addressed by ADDRG)
DIH Input 1 RAM 2-bit data write input addressed by ADDRH (read output is addressed by ADDRH)
ADDRA Input 6 Read port A address input
ADDRB Input 6 Read port B address input
ADDRC Input 6 Read port C address input
ADDRD Input 6 Read port D address input
ADDRE Input 6 Read port E address input
ADDRF Input 6 Read port F address input
ADDRG Input 6 Read port G address input
ADDRH Input 6 Read/write port H address input
WE Input 1 Write Enable
WCLK Input 1 Write clock (reads are asynchronous)

Design Entry Method

Instantiation Yes
Inference Recommended
IP Catalog No

This element can be inferred by some synthesis tools by describing a RAM with a synchronous write and asynchronous read capability. Consult your synthesis tool documentation for details on RAM inference capabilities and coding examples. Xilinx suggests that you instantiate this component if you have a need to implicitly specify the RAM function, or if you need to manually place or relationally place the component.

If synchronous read capability is desired, the outputs can be connected to an FDRE/FDSE (FDCE/FDPE if asynchronous reset is needed) in order to improve the output timing of the function. However, this is not necessary for the proper operation of the RAM. If you want to have the data clocked on the negative edge of a clock, an inverter can be described on the clock input to this component. This inverter will be absorbed into the block during implementation and set as the IS_WCLK_INVERTED attribute giving the ability to write to the RAM on falling clock edges.

If instantiated, the following connections should be made to this component:
  • Connect the WCLK input to the desired clock source

  • Connect the DIA–DIH inputs to the data source to be stored

  • Connect the DOA–DOH outputs to an FD* D input or other appropriate data destination, or leave unconnected if not used

  • Connect the WE clock enable pin to the proper write enable source in the design

  • Connect the ADDRH bus to the source for the read/write addressing

  • Connect the ADDRA–ADDRG buses to the appropriate read address connections

The optional INIT_A–INIT_H attributes let you specify the initial memory contents of each port using a 64-bit hexadecimal value. The INIT value correlates to the RAM addressing by the following equation: ADDRy[z] = INIT_y[z]. For instance, if the RAM ADDRC port is addressed to 00001, then the INIT_C[1] values would be the initial values shown on the DOC port before the first write occurs at that address. If left unspecified, the initial contents will default to all zeros.

Available Attributes

Attribute Type Allowed Values Default Description
INIT_A HEX Any 128-bit value All zeros Specifies the initial contents of the RAM on port A.
INIT_B HEX Any 128-bit value All zeros Specifies the initial contents of the RAM on port B.
INIT_C HEX Any 128-bit value All zeros Specifies the initial contents of the RAM on port C.
INIT_D HEX Any 128-bit value All zeros Specifies the initial contents of the RAM on port D.
INIT_E HEX Any 128-bit value All zeros Specifies the initial contents of the RAM on port E.
INIT_F HEX Any 128-bit value All zeros Specifies the initial contents of the RAM on port F.
INIT_G HEX Any 128-bit value All zeros Specifies the initial contents of the RAM on port G.
INIT_H HEX Any 128-bit value All zeros Specifies the initial contents of the RAM on port H.
IS_WCLK_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the WCLK pin.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

Verilog Instantiation Template

Related Information

  • Versal Adaptive SoC Configurable Logic Block Architecture Manual (AM005)