IOBUF_ODDR - 2025.1 English - Primitive: Input/Output Buffer with ODDR MUX - UG1485

Versal Architecture Premium Series Libraries Guide (UG1485)

Document ID
UG1485
Release Date
2025-09-17
Version
2025.1 English

Primitive: Input/Output Buffer with ODDR MUX

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: BIDIR_BUFFER
Sheet.1 IOBUF IOBUF_ODDR Sheet.2 I/O to/from device pad I/Oto/from device pad Dynamic connector path37 path39 Sheet.6 path37-1 path39-6 Dynamic connector.5 path44 path46 Sheet.12 path44-5 path46-9 Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 path68 path70 Sheet.22 path75 path77 path85 path87 text89 I_0 I_0 path85-1 path87-8 text89-0 I_1 I_1 text89-0-6 C C Sheet.32 O path96 path98 O Sheet.35 3-state input 3-state input Connector Dot.1 path121 path123 text125 T T path716 Sheet.41 X27139-091922 X27139-091922

Introduction

The IOBUF_ODDR primitive is needed when bidirectional signals require both an input buffer and a 3-state output buffer with an active-High 3-state T pin. The IOBUF_ODDR provides the unregistered ODDR MUX. A logic-High on the T pin disables the output buffer. When the output buffer is 3-stated (T = High), the input buffer and any on-die receiver termination (uncalibrated or DCI) are ON. When the output buffer is not 3-stated (T = Low), any on-die receiver termination (uncalibrated or DCI) is disabled.

I/O attributes that do not impact the logic function of the component such as IOSTANDARD, DRIVE and SLEW should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).

Port Descriptions

Port Direction Width Function
C Input 1 Clock controlled ODDR MUX select
DCITERMDISABLE Input 1 Control to enable/disable DCI termination. This is generally used to reduce power in long periods of an idle state.
I_0 Input 1 Parallel data input 0
I_1 Input 1 Parallel data input 1
IBUFDISABLE Input 1 Disables input path through the buffer and forces to a logic Low. This feature is generally used to reduce power at times when the I/O is idle for a period of time.
IO Inout 1 Bidirectional port to be connected directly to top-level inout port.
O Output 1 Output path of the buffer.
OSC<3:0> Input 4 Offset cancellation value
OSC_EN Input 1 Offset cancellation enable
T Input 1 3-state enable input signifying whether the buffer acts as an input or output.
VREF Input 1 Vref input

Design Entry Method

Instantiation Yes
Inference Recommended
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
SIM_INPUT_BUFFER_OFFSET DECIMAL -50 to 50 0 Offset value for simulation purposes.
USE_IBUFDISABLE STRING "FALSE", "T_CONTROL", "TRUE" "FALSE" Set this attribute to "TRUE" to enable the IBUFDISABLE pin.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

Verilog Instantiation Template