Primitive: General Clock Buffer with Clock Enable
- PRIMITIVE_GROUP: CLOCK
- PRIMITIVE_SUBGROUP: BUFFER
Introduction
This design element is a general clock buffer with a single gated
input. When clock enable (CE) is Low (inactive), its O output is 0.
When CE is High, the I input is transferred to the O
output.
Logic Table
Inputs |
Outputs |
I |
CE |
O |
X |
0 |
0 |
I |
1 |
I |
Port Descriptions
Port |
Direction |
Width |
Function |
CE |
Input |
1 |
Clock buffer active-High enable.
|
I |
Input |
1 |
Buffer input.
|
O |
Output |
1 |
Buffer output.
|
Design Entry Method
Instantiation |
Recommended |
Inference |
Yes |
IP and IP Integrator Catalog |
No |
Available Attributes
Attribute |
Type |
Allowed Values |
Default |
Description |
CE_TYPE |
STRING |
"SYNC", "ASYNC", "HARDSYNC" |
"SYNC" |
Specifies whether the enable should be synchronous
(glitch-free) or asynchronous (no input clock switching
necessary). Versal devices have a an optional hardened
synchronizer circuit that can be enabled by using the
HARDSYNC setting. |
IS_CE_INVERTED |
BINARY |
1'b0 to 1'b1 |
1'b0 |
Specifies use of the programmable inversion on the CE pin. |
IS_I_INVERTED |
BINARY |
1'b0 to 1'b1 |
1'b0 |
Specifies use of the programmable inversion on the I pin. |
SIM_DEVICE |
STRING |
"VERSAL_PREMIUM", "VERSAL_PREMIUM_ES1", "VERSAL_PREMIUM_ES2"
|
"ULTRASCALE" |
Set the device version |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFGCE: General Clock Buffer with Clock Enable
-- Versal Premium series
-- Xilinx HDL Language Template, version 2024.1
BUFGCE_inst : BUFGCE
generic map (
CE_TYPE => "SYNC", -- ASYNC, HARDSYNC, SYNC
IS_CE_INVERTED => '0', -- Programmable inversion on CE
IS_I_INVERTED => '0', -- Programmable inversion on I
SIM_DEVICE => "VERSAL_PREMIUM" -- VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2
)
port map (
O => O, -- 1-bit output: Buffer
CE => CE, -- 1-bit input: Buffer enable
I => I -- 1-bit input: Buffer
);
-- End of BUFGCE_inst instantiation
Verilog Instantiation Template
// BUFGCE: General Clock Buffer with Clock Enable
// Versal Premium series
// Xilinx HDL Language Template, version 2024.1
BUFGCE #(
.CE_TYPE("SYNC"), // ASYNC, HARDSYNC, SYNC
.IS_CE_INVERTED(1'b0), // Programmable inversion on CE
.IS_I_INVERTED(1'b0), // Programmable inversion on I
.SIM_DEVICE("VERSAL_PREMIUM") // VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2
)
BUFGCE_inst (
.O(O), // 1-bit output: Buffer
.CE(CE), // 1-bit input: Buffer enable
.I(I) // 1-bit input: Buffer
);
// End of BUFGCE_inst instantiation
Related Information
-
Versal
Adaptive SoC Clocking Resources Architecture Manual (AM003)