Vivado Project - 2025.2 English - UG1483

The HDL Netlist and IP Catalog compilation targets also generate an example Vivado project, which represents an integration of the results of Code Generation.

HDL Netlist

For the HDL Netlist compilation target, the Vivado project sets the module designed in Vitis Model Composer as the top-level and includes instances of IP. Also, if Create testbench is selected in the Vitis Model Composer Hub block, it adds a test bench and stimulus files (*.dat) to the project.

IP Catalog

For the IP Catalog compilation target, an example project is created with the following features:

• The IP generated from Model Composer is in the IP catalog associated with the project. This is available for the RTL flow and the IP integrator-based flow.
• The design includes an RTL instantiation of IP called <ip>_0 underneath <design>_stub. This indicates how to instantiate such an IP in the RTL flow
• The design includes an RTL test bench called <design>_tb that also instantiates the same IP in the RTL flow.

• If the selected part in this example is a Zynq 7000 SoC, the project also includes an example IP integrator diagram with a Zynq 7000 subsystem. For all other parts, a MicroBlaze™ -based subsystem is created.