To ensure that the HDL files generated by Vitis Model Composer work correctly in hardware, you must close timing. To help accelerate this process, timing analysis is integrated into Model Composer.
Timing analysis allows you to perform static timing analysis on the HDL files generated from Model Composer, either Post-Synthesis or Post-Implementation. It also provides a mechanism to correlate the results of running the AMD Vivado™ Timing Engine on either the Post-Synthesized netlist or the Post Implementation netlist with the Model Composer model in Simulink® . Thus, you do not have to leave the Simulink® modeling environment to close timing on the DSP sub-module of the design.
Invoking timing analysis on a compilation target displays a table of paths with columns for timing slack, path delay, and other details. This is the Timing Analyzer table.
You can sort the contents of the table using any of the column metrics such as slack, etc. Also, cross probing is enabled between the table entries and the Simulink model. This accelerates finding and fixing timing failures in the model. You can cross probe between the Timing Analyzer table and the Simulink model by selecting/clicking a row in the table. This highlights the corresponding path in the model. The path highlights in red if the path corresponds to a timing violation; otherwise it highlights in green.