Clock and clock enables appear in pairs throughout the HDL. Typical clock names
are clk_1, clk_2,
and clk_3, and the names of the companion clock
enables are ce_1, ce_2, and ce_3 respectively. The name
tells the rate for the clock/clock enable pair; logic driven by clk_1 and ce_1 runs at the system (that
is, fastest) rate, while logic driven by (say) clk_2
and ce_2 runs at half the system rate. Clocks and
clock enables are not driven in the entity or module named <design> or any
subsidiary entities. Instead, they are exposed as top-level input ports.
The names of the clocks and clock enables in Vitis Model Composer HDL suggest that clocking is completely general, but
this is not the case. To illustrate this, assume a design has clocks named clk_1 and
clk_2, and companion clock enables named ce_1 and
ce_2 respectively. You might expect that working
hardware can be produced if the ce_1 and ce_2 signals are tied high, and clk_2 are driven by a clock signal whose rate is half that of clk_1. For most Model Composer designs this does not work.
Instead, clk_1 and clk_2 must be driven by the same clock, ce_1 must be tied high, and ce_2 must
vary at a rate half that of clk_1 and clk_2.