Vitis Model Composer lets you build device-specific hardware designs directly in a flexible high-level system modeling environment. In a Model Composer design, signals are not simply bits. They can be signed and unsigned fixed-point numbers. Design changes automatically translate into appropriate changes in signal types. Blocks are not simply stand-ins for hardware. They respond to their surroundings, automatically adjusting the results they produce and the hardware they become.
Vitis Model Composer allows you to compose designs from a variety of ingredients. You can use data flow models, traditional hardware description languages (VHDL and Verilog), and functions derived from the MATLAB programming language side-by-side. You can simulate and synthesize them together into working hardware. Vitis Model Composer HDL block simulation results are bit and cycle-accurate. This means simulation results exactly match the results in the hardware. Model Composer simulations are considerably faster than those from traditional HDL simulators, and results are easier to analyze.
| Model Composer HDL Blocksets | Describes the organization of Vitis Model Composer's HDL blocks in libraries, and how you can parameterize and use those blocks. |
| Signal Types | Describes the data types used by Model Composer and how the tool can automatically assign them. |
| Bit-True and Cycle-True Modeling | Specifies the relationship between the Simulink-based simulation of a Vitis Model Composer model and the behavior of the hardware generated from it. |
| Timing and Clocking | Describes how clocks are implemented in hardware, and how you control their implementation within Vitis Model Composer. Explains how Model Composer translates a multirate Simulink model into working clock-synchronous hardware. |
| Synchronization Mechanisms | Describes mechanisms that can be used to synchronize data flow across the data path elements in a high-level Vitis Model Composer design, and describes how control path functions can be implemented. |
| Block Masks and Parameter Passing | Explains how parameterized systems and Subsystems are created in Simulink. |