Specifying PLIOs in Model Composer Designs - 2025.2 English - UG1483

Vitis Model Composer supports specifying the PLIO width using the AIE PLIO block. You can also make external stream connections across the AI Engine to PL boundary.

Figure 1. AIE Signal Spec

Specifying PLIO width at the boundary of the AI Engine subsystem can affect the throughput of data between the AI Engine and PL domains. You can also set the constraints for the PLIO block using its constraint manager.

Figure 2. Block Parameters: AIE PLIO

From the Parameters tab in the AIE Signal Spec block, you can select the available PLIO width options from the drop-down menu.

Consider the following example where an AIE Signal Spec block is connected at the boundary of the AI Engine subsystem.

By default, the PLIO width is set to auto. Other available options are: 32, 64, and 128.

Figure 4. Block Parameters: AIE PLIO Width

After specifying the PLIO width as 64 and 128 for the two AIE PLIO blocks in the example, the GUI updates as follows.

Figure 5. AIE Signal Spec Blocks Updated

adf::input_plio PL_AIE_IN;
adf::output_plio AIE_PL_OUT;
 
   Subsystem() {
      PL_AIE_IN = adf::input_plio::create("PL_AIE_IN",
            adf::plio_64_bits,
            "./data/input/PL_AIE_IN.txt");
 
      AIE_PL_OUT = adf::output_plio::create("AIE_PL_OUT",
            adf::plio_128_bits,
            "AIE_PL_OUT.txt");
 
 adf::connect< > (PL_AIE_IN.out[0], mygraph.PL_AIE_IN);
 adf::connect< > (mygraph.AIE_PL_OUT, AIE_PL_OUT.in[0]);