After creating a high-level graphical design using blocks from the Vitis Model Composer AI Engine library, simulate it interactively in the Simulink environment. This process ensures the functional correctness of the design using the native Simulink functional simulator and displays the results on scopes and graphical displays. Compilation and execution times are generally short at this stage. This helps you to quickly verify the functionality and iterate over the design until you meet the specification requirements. You can then use the functionally verified design to generate the dataflow graph using the Vitis Model Composer Hub block. You can verify the dataflow graph using various execution targets which Vitis Model Composer supports to simulate your AI Engine application. You can do this at different levels of abstraction, accuracy, and speed.
This section discusses following topics in detail:
- Running Simulink Simulation
- Code Generation
- Verifying the generated dataflow graph