Simulation involves compiling the design and checking for any design rule violations, then executing the design to produce the outputs. You can define the inputs of the design using any Simulink source blocks. Analyze the output either by logging the data to the workspace, or by viewing the results using a scope, spectrum analyzer, or display block.
Vitis Model Composer provides two MATLAB utilities xmcVitisRead and xmcVitisWrite. Use these to directly read or write data from or to files formatted for AIE Simulator and/or x86 Simulator. For more information on using these utilities, refer to AI Engine Utilities.
Clicking the Simulate model icon in the Simulink simulation tool bar, compiles all the kernels and graphs in the design. You can monitor the status from the Progress window, which displays after simulation begins (see the following figure).
The Progress window
displays only when you are compiling a design for the first time. When you simulate the
model again, Model Composer uses the cached entry for the block to initiate the
simulation faster. For example, assume you have three kernels (add2, add3, add4) in your design and you run the simulation for the first time. In
that case, the simulation compiles all three kernels. When you change the add3 kernel code and try to simulate again, only the
changed add3 kernel gets re-compiled and the cached
entries for add2 and add4 are used for faster simulation.
To manage the simulation cache in Model Composer, use the commands described in Managing the HLS Block Cache from the MATLAB command prompt.
When simulation is complete, you can review the results by connecting any of the Simulink sink blocks to appropriate points in your design.