To ensure that the HDL files generated by Vitis Model Composer fit into your target device, you might need to analyze the resources being used. To help accelerate this process, resource analysis is integrated into Model Composer.
Resource analysis allows you to determine the number of look-up tables (LUTs), registers, DSP48s (DSPs), and block RAMs (BRAMs) used by your model. The analysis is performed either Post-Synthesis or Post-Implementation and provides a mechanism to correlate the resources used in the AMD Vivado™ tools with the Model Composer model in Simulink® . This means you can investigate and identify areas of excessive resource use without leaving the Simulink modeling environment..
Invoking resource analysis on a compilation target (for example, IP catalog) displays a table of blocks and hierarchies. This is the Resource Analysis table and it shows LUT, Register, DSP, and block RAM resource usage.
You can sort the contents of the table using any of the column metrics such as DSPs, etc. Also, cross probing is enabled between the table entries and the Simulink model to accelerate finding and fixing excessive resource usage in the model. You can cross probe between the Resource Analysis table, and the Simulink model by selecting (clicking) a row in the table. This highlights the corresponding block, or hierarchy in the model in yellow.