Register the inputs and outputs of your design. You can do this by placing one or more Delay blocks with latency 1, or Register blocks, after Gateway In and before Gateway Out blocks. The following figure shows this. Selecting any of the Register block features adds hardware.
Double registering the I/Os can also be beneficial. You can do this by instantiating two separate Register blocks, or by instantiating two Delay blocks, each having latency 1. This lets you pack one register into the IOB and place the other beside the logic in the FPGA fabric. A Delay block with latency 2 does not give the same result. This is because the block with a latency of 2 is implemented using an SRL32 and cannot be packed into an IOB.