Performing Standard Hardware Co-Simulation - 2025.2 English - UG1483

If you are performing the standard (non-burst mode) hardware co-simulation, your Simulink mode contains a JTAG hardware co-simulation block. Model Composer creates this block automatically when it finishes compiling your design into an FPGA bitstream (see Compiling a Model for Hardware Co-Simulation). The block is stored in a Simulink library with the following file name:

<design_name>_hwcosim_lib.slx

The hardware co-simulation block moves into your Simulink model when compilation completes. In the following procedure, you need to wire up th block in your Simulink model to perform hardware co-simulation.

Figure 1. Hardware Co-Simulation Block

To perform the standard hardware co-simulation:

1. Connect the hardware co-simulation block to the Simulink blocks that supply its inputs and receive its outputs.
   
   
2. Double-click the hardware co-simulation block to display the properties dialog box for the block.
   
   
3. Fill out the block parameters in the properties dialog box.

   See Block Parameters for the JTAG Hardware Co-Simulation Block for block properties descriptions.

4. To set up the board for performing JTAG hardware co-simulation, connect a cable to the board’s JTAG port.

   Setting Up a KC705 Board for JTAG Hardware Co-Simulation describes the setup procedure for a JTAG hardware co-simulation, using a KC705 board as an example.

5. In the Simulink model, simulate the model and the hardware by clicking the Run button on the Simulation tab.
   
   

   Running the simulation simulates both the Model Composer design (or subsystem) in your Simulink model and the AMD device on your target board. You can then examine and compare the results of the simulations to determine if the design implemented in hardware will operate as expected.