Performing Burst Mode Hardware Co-Simulation - Performing Burst Mode Hardware Co-Simulation - 2026.1 English - UG1483

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2026-06-23
Version
2026.1 English

To perform the burst mode hardware co-simulation, execute the MATLAB M-code test bench that was generated automatically during compilation. (Refer to Compiling a Model for Hardware Co-Simulation.)

The test bench is in the Target directory that you specified when the design was compiled for the hardware co-simulation compilation target.

The test bench uses the following naming convention:

  • If you compiled the top-level design, the name of the test bench is as follows:
    <design_name>_hwcosim_test.m
  • If you compiled a subsystem of the design, the name of the test bench is as follows:
    <design_name>_<sub_system>_hwcosim_test.m
    Note: If your board contains an AMD Zynq™ SoC device, you must install the AMD Vitis™ unified software platform with the AMD Vivado™ Design Suite to perform hardware co-simulation.

Use the following steps to perform burst mode hardware co-simulation:

  1. Set up the board for performing JTAG hardware co-simulation.
  2. Run the test bench script from the MATLAB console.
    1. Open the MATLAB console.
    2. Change directory to the HDL subsystem source directory (<target_directory>/ip/<hdl_subystem>/src).
    3. Run the script by name

    The script runs the Simulink model to determine the stimulus data driven to the AMD Gateway In blocks (from the other Simulink source blocks or MATLAB variables), and captures the expected output produced by the AMD block design (BD), and exports the data to the Target directory as these separate data files:

    <design_name>_<sub_system>_<port_name>.dat

    The test bench then compares actual to expected outputs.

    If the test fails, the console prints an error message, and the failing comparisons output in this file:

    <design_name>_<sub_system>_hwcosim_test.result