Typically, the AI Engine array runs at a higher clock frequency (between 1 GHz and 1.25 GHz) than the internal Programmable Logic. Within the AI Engine core the streaming data-width is 32-bit. Between the AI Engine interface tile and PL interface, the streaming data-width is 64-bit by default. To balance throughput between the AI Engine and PL, pipeline enough data by selecting wider stream data paths for PL blocks. For example, to use an AI Engine array running at 32 bits / 1 GHz rate to its full potential, PL blocks can use either of the following rates:
- 64 bits / 500 MHz rate
- 128 bits / 250 MHz rate and so on
The AI Engine interface tile automatically sequentializes wider (>32 bits) stream data into 32-bit streams.