Vitis Model Composer does not replace hardware description language (HDL)-based design, but does makes it possible to focus your attention only on the critical parts. By analogy, most DSP programmers do not program exclusively in assembler; they start in a higher-level language such as C. They write assembly code only when necessary to meet performance requirements.
As a general rule, if your design requires managing internal hardware clock (for example, DDR memory or phased clocking), implement it using HDL. You can implement the less critical portions of the design in Model Composer, and then connect the HDL and Model Composer portion. Usually, most portions of a signal processing system do not need this level of control, except at external interfaces. Model Composer provides mechanisms to import HDL code into a design that are of particular interest to the HDL designer (refer to Importing HDL Modules).
Another feature of interest to HDL designers is Vitis Model Composer’s ability to automatically generate an HDL test bench, including test vectors. Refer to HDL Testbench for more information.
Finally, the hardware co-simulation interfaces described in Using Hardware Co-Simulation let you run a design in hardware under the control of Simulink. This brings the full power of MATLAB and Simulink to bear for data analysis and visualization.