Vitis Model Composer extends Simulink to enable hardware design. It provides high-level abstractions that can automatically compile into an FPGA. Although the arithmetic abstractions suit Simulink (discrete time and space dynamical system simulation), Model Composer also provides access to features in the underlying FPGA.
The more you understand a hardware realization (for example, how to exploit parallelism and pipelining), the better the implementation you can create. Using IP cores makes it possible to have efficient FPGA designs that include complex functions like FFTs. Model Composer also allows you to refine a model to more accurately fit the application.
Notes throughout the Model Composer documentation explain how system parameters help you exploit hardware capabilities.