Gateway Ins and Gateway Out blocks tagged as AXI4-Lite registers map to different 32-bit registers within a Memory Map, as shown in following Schematic.
The schematic below is an example of mapping to a single AXI4-Lite interface, assuming all gateways have the same interface name. In a schematic with multiple AXI4-Lite interfaces, each group of gateways with the same interface name maps to a separate AXI4-Lite interface.
As shown in the preceding diagram, module example_dds_inf_axi_lite_interface is inserted into the design RTL. This
drives the config_tvalid and config_tdata ports of the Model Composer design. At the top level, the
tool exposes a slave AXI4-Lite Interface. Address
decoding occurs within this module. The config_tvalid
and config_tdata ports are driven based on the address
obtained from the processor.
The number of AXI4-Lite interface
registers and the offset specifications of each AXI4-Lite register determines the number of bits required for addressing
(s_axi_araddr and s_axi_awaddr). Module generation provides enough bits to uniquely decode
each register. In this example, there are two Gateways – phase_data and phase_valid. Each port is
assigned an address offset of 0x0000 & 0x0004. Hence three address bits are
allocated.