Managing Multiple AXI4-Lite Interfaces - 2025.2 English - UG1483

Vitis Model Composer User Guide (UG1483)
Document ID
UG1483
Release Date
2025-11-20
Version
2025.2 English

Model Composer supports creation of IP with multiple AXI4-Lite interfaces. You can group Gateway In and Gateway Out blocks into different AXI4-Lite interfaces. This feature can be used in Multiple Clock designs as well. Software drivers are also provided.

Use the Interface Name control for the Gateway In/Out blocks associated with the interface to assign a name to an AXI4-Lite interface.

Gateway In and Gateway Out blocks with the same Interface Name group into one AXI4-Lite Interface. An Interface Name must begin with a lower case alphabetic character, and can only contain alphanumeric characters (lowercase alphabetic) or an underscore ( _ ). Having the same Interface Name across multiple clock domains is not supported.

Figure 1. Interface Name

You can use the IP Catalog or the HDL Netlist compilation type to generate the netlist.

If you specify the HDL Netlist compilation type in the Vitis Model Composer Hub block, then elaborate the design in Vivado, it creates two AXI4-Lite Decoders. This is shown in the red rectangle in the following figure.

Figure 2. AXI4-Lite Decoders

If you specify the IP Catalog compilation type in the Vitis Model Composer Hub block, the flow generates an example BD with multiple AXI4-Lite interfaces and an aresetn signal.

The naming convention for an interface is:


<clock domain name/design name>_<interface name>_s_axi
Figure 3. Example BD Generated by Your Tool

To generate a document describing the IP, select Create interface document on the Analyze tab of the Vitis Model Composer Hub block. Do this before compiling.

Figure 4. Create Interface Document

Access the document the same way you access the document for any other Vivado IP. Double-click the IP in the Vivado schematic, then select Documentation > Product Guide.

Figure 5. Accessing Documents

A document (HTML file) opens (see example below).

Figure 6. Sample Document

This document contains a section on the Memory Map for the IP. If you selected Auto assign address offset in the Gateway In or Gateway Out port for the AXI4-Lite interfaces, you can find out the address offset the different interfaces are mapped to.

Figure 7. Memory Map

Software Drivers are automatically generated and packaged as well in the AMD Vitis™ software platform. The documentation for the software drivers is in the Vitis environment.