The simulation semantics for M-Hwcosim differ from those used during hardware co-simulation in a Model Composer block diagram. Specifically, the M-Hwcosim simulation semantics are more flexible and can emulate the simulation semantics used in the block-based hardware co-simulation.
The block-based hardware co-simulation imposes a rigid simulation semantic. This means that before advancing a clock cycle, all the input ports of the hardware co-simulation are written to. Next all the output ports are read and the clock is advanced. In M-Hwcosim, you control when ports are read or written during scheduling. For example you can create a program that only writes data to certain ports on every other cycle, or only reads the outputs after a certain number of clock cycles. This flexibility allows you to optimize data transfer for improved performance.