AMD Vitis™ Model Composer provides the HDL blockset in AMD toolbox that enables the use of the MathWorks model-based Simulink design environment for FPGA design. You do not need previous experience with AMD FPGAs or RTL design methodologies to use the Model Composer HDL blockset. Designs are captured in the DSP-friendly Simulink modeling environment using the HDL blockset. You can then import the AMD Vitis™ Model Composer design into a Vivado IDE project using the IP catalog.
Figure 1. Model Composer HDL Design
Refer to the Vitis Model Composer Tutorials for hands-on lab exercises and step-by-step instruction on how to:
- Create a model using HDL blockset
- Import the model into a Vivado IDE project.