Throughput of a system is one of its most important design criteria. For example, if your system processes HD video frames (1920×1080) at 30 frames per second, it requires a throughput of 62,208,000 pixels per second (1920x1080x30). If you process one pixel per clock (initiation interval = 1 [ii=1]), your device must run at over 62.2 MHz to meet throughput requirements. If your requirements change, and you need to process a 4K video frame at 60 frames per second. Now the required throughput of the application is 497,664,000 pixels per second (3840x2160x60), and you need to clock your device at over 497 MHz.
However, in practice it can be difficult to achieve an initiation interval of one (II=1). Therefore, to achieve the desired throughput, you need to clock the device at even higher rates. In applications such as wireless communications, the clock frequencies required for the desired throughput can surpass the maximum clock frequency allowed for a device.
Sometimes you need to increase the throughput of your design, without increasing the clock frequency that your device is operating at. This can be to operate at a clock frequency below the maximum allowed for a device, or to curtail power consumption. In these cases, you can take advantage of the programmable logic nature of AMD FPGAs, and use parallelization techniques to process more samples per clock. Throughput control in Vitis Model Composer allows you to do that without making structural changes to your design in Simulink.