AMD Vitis™ Model Composer is a model-based design tool that enables rapid design exploration within the Simulink® environment. It accelerates the path to production on AMD devices through automatic code generation. Model Composer provides a library of performance-optimized blocks for design and implementation of algorithms on AMD devices using HDL, HLS, and AI Engine blocks.
You can express algorithms with blocks from these libraries, and with custom user-imported blocks, without focusing on implementation specifics. You can also leverage all the capabilities of Simulink's graphical environment for algorithm design, simulation, and verification.
The AI Engine library in Vitis Model Composer contains blocks to import kernels and graphs which can be targeted to the AI Engine portion of AMD Versal™ devices. Also included is a set of complex AI Engine DSP building blocks related to FIR, FFT, DDS, and Mixers. The tool transforms your AI Engine design specification into a top level connected graph to implement AI Engine-based devices.
The HDL library in Vitis Model Composer contains DSP building blocks. These blocks include the basic element blocks such as adders, multipliers, and registers. The library also includes a set of complex DSP building blocks such as FFTs, filters, and memories. These blocks leverage the AMD IP core generators to deliver optimized results for the selected device.
The HLS library in Vitis Model Composer offers predefined blocks including functional blocks for Math, Linear Algebra, Logic, and Bit-wise operations. The tool transforms your algorithmic specifications to production-quality implementation through automatic optimizations that extend the AMD High Level Synthesis technology.
Vitis Model Composer allows you to co-simulate a heterogeneous system consisting of AI Engines and PL. You can directly use optimized AI Engine, HLS, or HDL blocks from the Simulink Library Browser, or import code as blocks. You can connect these blocks in Simulink to perform functional simulation.
The hardware validation flow in AMD Vitis Model Composer provides a methodology to verify AI Engine and/or PL-based applications on AMD hardware. Vitis Model Composer generates a hardware image. You can run this on a board to verify whether the results from hardware match the functional simulation output.
The rest of this document describes information on features and specific blocks related to the following categories:
- HDL Library
- Refer to HDL Library
- HLS Library
- Refer to HLS Library
- AI Engine Library
- Refer to AI Engine Library
- Hardware Validation Flow
- Refer to Hardware Validation Flow for AI Engines and PL.
- Co-Simulation of AI Engine and PL
- Refer to Connecting AI Engine and Non-AI Engine Blocks.