To include a Vitis Model Composer model in a larger design, you must follow these design rules:
- Rule 1
- No Gateway specifies an IOB/CLK location.
You must set IOB timing constraints to: none.
- Rule 2
- You must instantiate appropriate buffers in the top-level HDL code if any I/O ports from the Model Composer design are required to be ports on the top-level design.