Insert pipeline registers wherever possible and reasonable. Deep pipelines are efficiently implemented with the Delay blocks because the SRL32 primitive is used. If an initial value is needed on a register, use the Register block. If an SRL32 input path fails timing, place a Register block before the Delay block and reduce the Delay block latency by one cycle. This allows the router more flexibility to place the Register and Delay block (SRL + Register) away from each other. This approach maximizes the margin for the routing delay of this path.
As the following figure shows, you can pipeline the Convert block with embedded register stages to guarantee maximum performance.
To achieve a more efficient implementation on some AMD blocks, you can select the Implement using behavioral HDL option. As shown below, if the delay on a Delay block is 32 or greater, AMD synthesis infers a SRLC32E (32-bit Shift-Register). This maps into a single LUT.
For block RAMs (BRAMs), use the internal output register. You do this by setting the latency from 1 (the default) to 2. This enables the block RAM output register.
When you are using DSP48E1s, use the input, output, and internal registers. For FIFOs, use the embedded registers option. Also, check all the high-level IP blocks for pipelining options.