When Vitis Model Composer invokes Vivado synthesis, it uses a disk cache to accelerate the iterative design process.
Vivado synthesis invokes when you perform Timing or Resource analysis, or when you export a Synthesized Checkpoint.
When you enable cache, each time your compilation generates an IP instance for synthesis and Vivado produces output products, the tools create a cache entry.
After cache population, if you create a new IP customization with identical properties, the IP is not synthesized again. Instead, the tool references the cache and copies the corresponding synthesis output into your design’s output directory. Because the IP instance is not re-synthesized, and this process is repeated for every IP referenced, output product generation is faster.
Multiple Simulink models on your system share the IP cache. If you reuse an IP in another design and customize it identically, with matching part and language settings, you can benefit from caching during compilation.
To find the location of the IP cache directory on your system, enter the
command xilinx.environment.getipcachepath on the
MATLAB command line. The full path to the IP
cache directory displays in the MATLAB command
window.
>> xilinx.environment.getipcachepath
ans =
C:/Users/your_id/AppData/Local/Xilinx/Sysgen/SysgenVivado/win64.o/ip
IP caching in Model Composer is similar to IP caching in the Vivado Design Suite. Refer to this link in the Vivado Design Suite User Guide: Designing with IP (UG896) for details. However, the IP cache for Model Composer designs is in a different location than the IP cache for Vivado projects.