You can generate a hardware image for designs with either of the following:
- Only AI Engine subsystems
- Both PL and AI Engine subsystems
- Only PL subsystems
To generate an image for hardware or hardware emulation, Vitis Model Composer supports the following base platforms:
-
vck190_base -
vck190_base_dfx -
vek280_base -
kv260_base -
vmk180_base
Using the Vitis Model Composer Hub block, you can create either a baremetal or Linux-based application for a hardware or a hardware emulation target. In hardware emulation, AMD Vivado™ simulator simulates the PL portions of the design and QEMU emulates the host code for the Arm® processor. The advantage of hardware emulation is that there is no need for a hardware board. However, hardware emulation is only an emulation of the hardware and is, in general, slower than running the design in hardware.
As part of hardware image creation, the tool collects the input data samples that feed into the design during simulation in Simulink. Similarly, it collects the output data samples from the design. The input and output data are packaged as part of the hardware image and downloaded to the hardware. The input data is fed into the design in hardware, the output data is collected and compared with the output data from simulation. The device processor performs this comparison. Unless something is wrong, the result matches bit by bit with the simulation output because Vitis Model Composer simulation is bit-accurate. The hardware runs independently of Vitis Model Composer. During the hardware run Vitis Model Composer and the hardware do not communicate.