Hardware Co-Simulation Overview - 2025.2 English - UG1483

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2025-11-20
Version
2025.2 English

The following figure provides a high-level overview of HWCosim. At the center of it is the device under test (DUT). The DUT is typically a piece of IP developed and tested within a Simulink test framework. It provides the stimulus and receives (and potentially evaluates) the response. In order to allow for Simulink to communicate with the DUT it needs to be embedded into the HWCosim wrapper consisting of the following components:

Figure 1. Hardware Co-Simulation Flow

Communication interface (JTAG)
Used for communications with the host PC, receiving the command messages and sending responses.
Command processor
Parses and executes command messages.
Memory-mapped AXI4-Lite register bank
Use write commands to set up the stimulus data in the register map, which is driving the inputs to the DUT. Similarly, use read commands to query the memory-mapped DUT outputs. Finally, use a run(x) command to the memory-mapped clock control register to trigger exactly "x" clock pulses on the DUT's clock input. Alternatively, use run(inf) to start the free-running clock mode and run(0) to turn the clock off.