HDL Library - HDL Library - 2026.1 English - UG1483

Vitis Model Composer User Guide (UG1483)

Document ID: UG1483
Release Date: 2026-06-23
Version: 2026.1 English

Overview
Navigating Content by Design Process
Introduction
What's New and Limitations
Supported MATLAB Versions and Operating Systems
Installation
Vivado License Tier
Post-Installation Tasks
Configure OS Libraries
Configure Bash Shell (Ubuntu Only)
Compiling AMD HDL Libraries
Managing the Model Composer Block Cache
Specifying Board Support in Model Composer
Hardware Co-Simulation Support
UNC Paths Not Supported
Recommended Display Resolution
HDL Library
Introduction
FIR Filter Generation
Support for MATLAB
Hardware Co-Simulation
System Integration Platform
Hardware Design Using the HDL Library
Design Flows Using Model Composer
Algorithm Exploration
Implementing Part of a Larger Design
Implementing a Complete Design
Note to DSP Engineers
Note to Hardware Engineers
System-Level Modeling in Vitis Model Composer
Model Composer HDL Blocksets
Signal Types
Floating-Point Data Type
AXI Signal Groups
Bit-True and Cycle-True Modeling
Timing and Clocking
Synchronization Mechanisms
Block Masks and Parameter Passing
Automatic Code Generation
Compiling and Simulating Using the Model Composer Hub
Compilation Results
Using the Constraints File
Multicycle Path Constraints
IOB Timing and Placement Constraints
The "Clock Enables" Multirate Implementation
IP Instance Caching
Vivado Project
HDL Testbench
Compiling MATLAB into an FPGA
Simple Selector
Simple Arithmetic Operations
Complex Multiplier with Latency
Shift Operations
Passing Parameters into the MCode Block
Optional Input Ports
Finite State Machines
Parameterizable Accumulator
FIR Example and System Verification
RPN Calculator
Example of disp Function
Importing a Model Composer HDL Design into a Bigger System
HDL Netlist Compilation
Integration Design Rules
Variant Subsystems and Vitis Model Composer
Defining a Variant Subsystem
Using a Variant Subsystem
Notes for Higher Performance FPGA Design
Review the Hardware Notes Included with Each Block Dialog Box
Register the Inputs and Outputs of Your Design
Insert Pipeline Registers
Use Saturation Arithmetic and Rounding Only When Necessary
Set the Data Rate Option on All Gateway Blocks
Pipeline for Maximum Performance
Other Things to Try
Using the FDATool in Digital Filter Applications
Multiple Independent Clocks Hardware Design
Grouping Blocks within a Clock Domain
HDL Blocks used to Create Asynchronous Clock Domains
Configuring the Vitis Model Composer Hub Block
Clock Propagation Algorithm
Debugging Clock Propagation
Debugging Multiple Clock Domain Signals
Code Generation
Known Issues
AXI Interface
AXI4-Stream Support in Model Composer
AXI4-Stream Blocks in Model Composer
AXI4-Lite Slave Interface Generation
AXI4-Lite Interface Synthesis in Vitis Model Composer
Configuring the Design for an AXI4-Lite Interface
Packaging the Design for Use in Vivado IP Integrator
Description of the Generated Results
Mapping to AXI4-Lite Interfaces
Managing Multiple AXI4-Lite Interfaces
Address Generation
Features of the Vivado IDE Example Project
Software Drivers
Known Issue in AXI4-Lite Interface Generation
Using Super Sample Rate (SSR) Blocks in Model Composer
Performing Analysis in Vitis Model Composer
Timing Analysis in Vitis Model Composer
Performing Timing Analysis
Cross Probing from the Timing Analysis Results to the Model
Accessing Existing Timing Analysis Results
Recommendations For Troubleshooting Timing Violations
Resource Analysis in Vitis Model Composer
Performing Resource Analysis
Cross Probing from the Resource Analysis Results to the Model
Accessing Existing Resource Analysis Results
Recommendations for Optimizing Resource Analysis
Using Hardware Co-Simulation
Compiling a Model for Hardware Co-Simulation
Performing Standard Hardware Co-Simulation
Performing Burst Mode Hardware Co-Simulation
M-Code Access to Hardware Co-Simulation
Compiling Hardware for Use with M-Hwcosim
M-Hwcosim Simulation Semantics
Data Representation
Interfacing to Hardware from M-Code
Automatic Generation of M-Hwcosim Testbench
Resource Management
M-Hwcosim MATLAB Class
Setting Up Your Hardware Board
Setting Up a KC705 Board for JTAG Hardware Co-Simulation
Hardware Co-Simulation Blocks
Block Parameters for the JTAG Hardware Co-Simulation Block
Hardware Co-Simulation Clocking
Clocking Modes
Burst Data Transfers for Hardware Co-Simulation
Hardware Co-Simulation Overview
Burst Data Transfer Mode
How to Use Burst Data Transfer Mode
Importing HDL Modules
Black Box HDL Requirements and Restrictions
Black Box Configuration M-Function
Language Selection
Specifying the Top-Level Entity
Defining Port Blocks
Adding New Ports
Obtaining a Port Object
Configuring Port Types
Configuring Bi-Directional Ports for Simulation
Configuring Port Sample Rates
Dynamic Output Ports
Black Box Clocking
Combinational Paths
Specifying VHDL Generics and Verilog Parameters
Black Box VHDL Library Support
Error Checking
Black Box API
SysgenBlockDescriptor Member Variables
SysgenBlockDescriptor Methods
SysgenPortDescriptor Member Variables
SysgenPortDescriptor Methods
Multiple Independent Clock Support on Black Box
Design Rule Checks on Port Connection
Configuring Port Sample Rates
Black Box Clocking
HDL Co-Simulation
Configuring the HDL Simulator
Co-Simulating Multiple Black Boxes
Black Box Configuration Wizard
Using the Configuration Wizard
Configuration Wizard Fine Points
Compilation Types for HDL Library Designs
HDL Netlist Compilation
Hardware Co-Simulation Compilation
IP Catalog Compilation
The IP Catalog Flow
Including a Testbench with the IP Module
Adding an Interface Document to the IP Module
Adding the Generated IP to the Vivado IP Catalog
Synthesized Checkpoint Compilation
Vitis Subsystem Compilation
Creating Your Own Custom Compilation Target
Creating Custom Compilation Targets
xilinx_compilation Base Class
Creating a New Compilation Target
Running the Helper Function
Modifying a Compilation Target
Adding an Existing Compilation Target
Saving a Custom Compilation Target
Removing a Custom Compilation Target
Base Class Properties and APIs
Vivado Project-Related Properties
Vivado IDE Project Generation-Related Functions
Design Info
Token-Related Properties and APIs
Examples of Creating Custom Compilation Targets
Example 1: Creating an Implementation Target
Example 2: Creating a Bitstream Target
AMD Waveform Viewer
Waveform Viewer Files
Opening the AMD Waveform Viewer
Adding Signals to the Waveform Viewer Display
Deleting Signals From the Waveform Viewer Display
Cross Probing Between the Waveform Viewer and the Model
Clearing the Waveform Viewer Display
Customizing the Display and Analyzing Waveforms
Tips for Working in the Waveform Viewer
Closing the Waveform Viewer
HLS Library
Introduction
Creating a Model Composer Design
Creating a New Model
Adding Blocks to a Model
Connecting Blocks
Working with Data Types
Working with Fixed-Point Data Types
Working with Half Data Types
Working with Data Type Expression
Managing Overflow
Saturate on Overflow
Configuring Overflow Warnings
Creating a Top-Level Subsystem Module
Importing C/C++ Code as Custom Blocks
Introduction
Using the xmcImportFunction Command
Importing C/C++ into Model Composer
Using Complex Types
Defining Blocks Using Function Templates
Function Templates for Data Types
Defining Customization Parameters
Pragmas for xmcImportFunction
XMC SUPPORTS_STREAMING
XMC BUFFER_DEPTH
XMC THROUGHPUT_FACTOR
Adding Your Library to Library Browser
Debugging Imported Blocks
Enable Debug Mode
Launching the Debug Tool
Setting a Breakpoint for the Imported Function
Connecting Debug to the MATLAB Process
xmcImportFunctionSettings Command Syntax
Generating Outputs
Introduction
Vitis Model Composer Hub
Controlling the Throughput of the Implementation
Introduction
Setting Throughput Factor from the Hub Block
Restrictions on Using Throughput Control
Understanding Throughput Control Through an Example
Defining the Interface Specification
Generating Packaged IP for Vivado
Generating C++ Code
Model Composer Log File
Simulating and Verifying Your Design
Introduction
Simulating in Simulink
Managing the HLS Block Cache
Verifying the C++ Code
Verifying the C/RTL Code
Select Target Device or Board
Device Chooser Dialog Box
AI Engine Library
Introduction
AI Engines
Programmable Logic and Processor Subsystem
AI Engine Kernels
AI Engine Graphs
Vitis Model Composer for AI Engine Development
Creating an AI Engine Design using Vitis Model Composer
Preparing the Kernels
Data Accessing Mechanisms
Runtime Parameter Specification
Importing AI Engine Code as a Block
Variable-Size Signals
Importing AI Engine Kernels
Non-Class-Based Kernels
Importing Buffer-Based Kernels
Importing Stream-Based Kernels
Importing an AI Engine Kernel with Runtime Parameters
Importing an AI Engine Kernel with Function Template
Template Specialization
Class-Based Kernels
Kernel Class with Default Constructor
Class Kernels with Parameterized Constructors
Constructor with Reference to an Array
Kernel with Class Templates
Kernels with Namespaces
Specifying Constraints
Core utilization factor (runtime<ratio>)
Kernel Location
Stack Location
Stack Size
Heap Size
Parameter Location
Buffer Location
HLS Kernel Frequency
Graph Bounding Box
Graph Stamp Location
PLIO Location
Importing AI Engine Graphs
Importing Kernels and Graphs as Source Blocks
AI Engine DSPLib
Bundled SSR Connectivity with Matrices
Setting Signal Size to Avoid Buffer Overflow
AI Engine Designs with Feedback Loops
Simulation and Code Generation
Running Simulink Simulation
Debugging AI Engine Code
Code Generation
Vitis Model Composer Hub Block for AI Engine Code Generation
Output Directory
Stream FIFO Depth Specification
PLIO Attributes
Specifying PLIOs in Model Composer Designs
Data File Layout
Specifying PLIO Frequency
Verification of AI Engine Code
Vitis Model Composer Hub Block for Verification
Profiling Statistics and Event Tracing
Viewing Results in the Vitis Analyzer
Plotting AIE Simulation Output Data and Calculating Throughput
Plotting AIE Simulation Internal Signals
Running Simulation using the Makefile
Hardware Validation Flow for AI Engines and PL
Introduction
High-Level Flow for Generating a Hardware Image
Setting up the Tool to Generate an Image File for Hardware Validation Flow
Running the Hardware Flow Outside the MATLAB Environment
Design Considerations
Connecting AI Engine and Non-AI Engine Blocks
AI Engine/Programmable Logic Integration
Connecting AI Engine and PL Subsystems
Interconnecting AI Engine and HDL Blocks
AIE to HDL
Setting the AIE to HDL Block
HDL to AIE
Setting the HDL-AIE Block
Interconnecting AI Engines and HLS Kernels
HLS Function versus HLS Kernel
Behavior of HLS Functions on Blocking Calls
Importing HLS Kernels
Importing Templatized Functions
Interconnect AI Engine and HLS Kernel Blocks
AIE to HLS Kernel
HLS Kernel to AIE
Vitis Subsystem Compilation
Connecting Source and Sink Blocks
Model Composer Utilities
AI Engine Utilities
xmcLibraryPath
xmcVitisRead
xmcVitisWrite
HDL Utilities
xilinx.analyzer
xilinx.environment.getcachepath and xilinx.environment.setcachepath
xilinx.resource_analyzer
xlfda_denominator
xlfda_numerator
vmcAnalyze
vmcValidate
vmcExport
vmcGetHubParams
vmchub_get_param
vmchub_set_param
Vitis Model Composer Hub Block Parameters
xlGetReOrderedCoeff
xlOpenWaveFormData
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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