HDL Co-Simulation - 2025.2 English - UG1483

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2025-11-20
Version
2025.2 English

This topic explains how to simulate a complete mixed language/mixed flow design that includes AMD HDL blocks, HDL modules, and a Simulink block design.

Model Composer simulates black boxes by:

  • Automatically launching an HDL simulator,
  • Generating additional HDL as needed (analogous to an HDL test bench),
  • Compiling HDL,
  • Scheduling simulation events,
  • Handling the exchange of data between the Simulink and the HDL simulator.

This is called HDL co-simulation.