To pass data between the src_domain and
dest_domain Subsystems, you can use any one of the
following logics:
- FIFO block
- Dual Port RAM block
- Register block
- Black Box block. You can use this to bring existing VHDL and Verilog files into a design. For more information about Black Box utility, refer to Importing HDL Modules.
These blocks configure themselves to be either synchronous single clock blocks or multiple clock blocks based on their context in the design. This design uses the FIFO block to cross the clock domains, as shown in the following figure.
Figure 1. Cross Domain FIFO Block
To complete the design, include the FIFO block at the top level to enable Code Generation.