Vitis Model Composer uses subsystems to group together blocks. You can also use subsystems to group blocks within a clock domain. You can then control clock settings for each subsystem by enabling multiple clocks on the HDL Settings tab of the Vitis Model Composer Hub block.
The preceding figure shows a clock domain Subsystem called src_domain. On the HDL Settings tab, the FPGA
clock period is (1000/368) ns (368 MHz) and the Simulink system period is 1 sec. This implies that an
advance of 1 Simulink second corresponds
to (1000/368) ns of FPGA clock.
Similarly, a subsystem called dest_domain includes another group of blocks representing
another clock domain. This Subsystem runs at an FPGA clock period of
1000/245 ns (245 MHz). The Simulink
system period is set to 368/245. This is done because the Simulink system period of the src_domain Subsystem is set to 1. Hence,
you normalize the System period from the faster src_domain.