Generating Packaged IP for Vivado - 2025.2 English - UG1483

Vitis Model Composer can automatically generate packaged IP for use in Vivado IP catalog. When Model Composer generates output for the IP catalog, it first writes the C++ code as described in Generating C++ Code. It then synthesizes RTL code from the C++ code. To do this:

1. Set the Export Type in the Model Composer Hub block to IP Catalog.
2. Click Apply to confirm any changes.
3. Click Export.

Model Composer displays a transcript window of the process.

When Vitis Model Composer has completed synthesizing the RTL, it launches Vivado to create and package the IP for the subsystem design.

Model Composer generates the following outputs from the algorithm:

• SystemC (IEEE 1666-2006, version 2.2)
• VHDL (IEEE 1076-2000)
• Verilog (IEEE 1364-2001)
• Report files created during synthesis, C/RTL co-simulation, and IP packaging.

When Vitis Model Composer finishes generating the packaged IP, you can find it in the project directory structure as shown in the following figure.

• The src folder is in the Export Directory specified by the Model Composer Hub.
• The Color_detection_comp folder is a Vitis HLS component. For more information refer to the Vitis High-Level Synthesis User Guide (UG1399).
• The syn and impl folders store the results of synthesis and implementation.
• The ip folder contains the packaged IP to add to the Vivado Design Suite IP catalog.

Figure 1. Packaged IP Folder

After Model Composer generates the packaged IP, you can import the .zip file archive in the <component_name>/hls/impl/ip folder into the Vivado IP catalog. You can use this in any Vivado Design Suite design, either as RTL IP, or in the IP integrator.

You can find the Synthesis Report in the generated file <component_name>/hls/synth/reports/<component_name>_csynth.rpt. The Synthesis Report includes details on the estimated performance and resource utilization of the RTL design synthesized by Model Composer. You can review this report to see the estimates and review your model.

Figure 2. Synthesis Report

For Model Composer models that specify AXI4-Lite Slave interfaces through the Interface Specification block, as discussed in Defining the Interface Specification, a set of software driver files is also created by Vitis HLS during the IP packaging process. These C driver files can be included in an SDK C project and used to access the AXI4-Lite Slave slave port. Model Composer writes the software driver files to directory <component_name>/hls/impl/ip/drivers. These are part of the packaged IP.

To add the IP into the Vivado IP catalog, from within the Vivado Integrated Design Environment (IDE), select Tools > Settings to open the Settings dialog box. Select the IP > Repository command, and add the Vitis HLS packaged IP as shown in the following figure.

Figure 3. Setting the IP Repository

After adding the path to the repository, the IP is added to the IP catalog as shown in the following figure. You can now use the IP in standard RTL designs, or in Vivado IP integrator block designs. For more information on working with IP and adding to the IP repository refer to the Vivado Design Suite User Guide: Designing with IP (UG896).

Figure 4. IP Catalog