The HDL Blockset in Model Composer includes a FIR Compiler block that targets the dedicated DSP48E1, DSP48E2, and DSP58 hardware resources in the 7 series, AMD UltraScale™ and AMD Versal™ devices respectively to create highly optimized implementations. Configuration options allow generation of single rate, interpolation, decimation, Hilbert, and interpolated implementations. You can use standard MATLAB® functions such as fir2 or the MathWorks FDA tool to create coefficients for the AMD FIR Compiler.
Figure 1. FDA Tool Example