- HDL and HLS subsystems can only have AXI4-Stream input and output ports. The AXI4-Stream input and output ports of the subsystem must have a
bit width that is a multiple of 8 bits, up to a maximum of 128 bits.
- Ensure that there are no extra outputs from the subsystem that are not in
the hardware implementation, such as debug outputs to monitor internal
signals.
- If the same input signal drives multiple blocks, signal multiplexing must
occur outside the hardware subsystem, so there are subsystem inputs for each
block input.
- Considerations for HLS Designs:
- You can only use HLS Kernel blocks to import HLS C/C++ code (for PL). The
Hardware Validation Flow does not support blocks from the HLS
library.
- The HLS Kernel must be in free-running mode. Do this by the including the
following pragma in the HLS function:
#pragma
HLS INTERFACE ap_ctrl_none port=return
- Ensure the bit width of the HLS Kernel input or output
that connects with the AI Engine matches the PLIO width of the AIE.
- Consideration for HDL Designs:
- The HDL part of the design must not be purely
combinational.