Debugging Multiple Clock Domain Signals - 2025.2 English - UG1483

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2025-11-20
Version
2025.2 English

You can use cross probing between the signal in the AMD Waveform Viewer and the Simulink diagram to aid the debugging process.

To add a signal to the Waveform viewer, right-click the signal in the model and select AMD Add To Viewer. Simulating the design launches the Waveform Viewer as shown in the following figure.

Figure 1. Waveform Viewer

All signals in same clock domain use a similar color. In the preceding figure: src_domain/Slice/Out1 and dest_domain/Relational/Out1 are in different clock domains.