You can use the Model Composer Hub block to control HDL Block icon display. To do this, use the Block Icon Display control in the HDL Analyze tab. From this tab, either select Normalized sample periods or Sample frequencies to help understand how clocks propagate in the design. For multiple-clock designs, Normalized sample periods use the smallest Simulink system period to normalize all sample periods in the design.
For Sample Frequencies, the port icon text display is the result of the following computation:
where FPGA clock period is the FPGA clock period specified in ns in the domain’s Clock Settings tab, and Simulink system period is the Simulink system period in seconds specified in the domain’s HDL Clock Settings tab.
The ratio of Simulink system period to FPGA clock period in each domain must be the same. This ensures that the simulation models the hardware relatively with respect to the blocks. If the ratio is incorrect, a warning highlights the issue, as shown in the following figure.