Vitis Model Composer supports heterogeneous designs that mix AI Engine and HDL subsystems and HLS Kernels. In these designs, data often flows between different “domain” subsystems (for example, from an AI Engine subsystem into an HLS Kernel implemented in PL).
To ensure these cross-domain connections are well-formed and supported in downstream flows, Vitis Model Composer enforces a validation rule on the blocks that are allowed between heterogeneous subsystems.
The following blocks are allowed between subsystems of different domains.
- HLS Kernel to AIE
- AIE to HLS Kernel
- HDL to AIE
- AIE to HDL
- Algebraic Loop Breaker
The Vitis Model Composer Hub block flags unsupported blocks between subsystems of different domains.