You must configure the Vitis Model
Composer Hub block to indicate that Code Generation must proceed for a multiple clock design.
This is indicated by turning on the Enable multiple
clocks check box on the HDL
Settings tab. This tells the code generation engine to get clock
information for the src_domain and dest_domain Subsystems
from each clockâs sub-tab. If you do not enable this check box is not enabled, the tool treats
the design as a single-clock design.