Configuring the Vitis Model Composer Hub Block - Configuring the Vitis Model Composer Hub Block - 2026.1 English - UG1483

You must configure the Vitis Model Composer Hub block to indicate that Code Generation must proceed for a multiple clock design. This is indicated by turning on the Enable multiple clocks check box on the HDL Settings tab. This tells the code generation engine to get clock information for the src_domain and dest_domain subsystems from each clock’s sub-tab. If you do not enable this check box, the tool treats the design as a single-clock design.