In the example_dds design, Gateway In and
Gateway Out blocks mark the boundary of the Cycle and Bit accurate FPGA portion of the
Simulink design. Control of the DDS Compiler frequency
is accomplished by “injecting” the correct value on the signals attached to the output port of
Gateway In’s called phase_valid and phase_data. This is accomplished by modifying the Interface Options as shown in the following figure for
the phase_valid block.
Notice the example specifies the Interface as a slave AXI4-Lite Interface in Model Composer. This means that it transforms to a top-level AXI4-Lite interface.
The following options are also of particular interest:
- Auto assign address offset
- (Enabled) Each Gateway is associated with a register within the AXI4-Lite Interface and this control specifies that Automatic assignment of address offsets take place in the design based on number of different Gateway Ins mapped to the AXI4‑Lite interface. Addresses are byte aligned to a 32-bit data width.
- Address offset
- (Disabled) This option is only enabled if Auto assign address offset is unchecked. It allows you to manually override the Address Offset.
- Interface Name
- Assigns a unique name to this
interface. You can use this name to differentiate between multiple AXI4-Lite interfaces in the design.Important: The Interface Name must be alphanumeric characters (lowercase alphabetic) or an underscore (_) only, and must begin with a lowercase alphabetic character. '
axi4_lite1' is acceptable, '1Axi4-Lite' is not. - Description
- The text you enter here appears in the "Interface Documentation" that automatically generates when you export the design to the Vivado IP catalog.
Configure the other Gateways in the design in a similar fashion.