In multiple clock hardware designs, compute the clock period of the port interface using the connected "clocked subsystem domain." By default, "synchronous system clock" source is used by all the ports, but for asynchronous clock hardware designs, it is necessary to explicitly specify the clock sources of every port (for example, if the output port clock is different than the block's input port clock).
SysgenPortDescriptor provides a method called setRate that you can use to
explicitly set the rate of a port.
Example:
port('<port_name>').setRate(1.0)