Vitis Model Composer supports bidirectional ports (or
inout ports) only during HDL netlist generation. They do not appear in the
Model Composer diagram. By default, bi-directional ports are driven with 'X' during
simulation. It is possible to overwrite this behavior by associating a data file to the port.
Guard this code, as you can only add bidirectional ports during the config_netlist_interface phase.
if (strcmpi(this_block.getConfigPhaseString,'config_netlist_interface'))
bidi_port = this_block.port('bidi');
bidi_port.setGatewayFileName('bidi.dat');
end
In the above example, the simulation uses a text file, bidi.dat to provide stimulation to the port. The data file must be a text file,
where each line represents the signal driven on the port at each simulation cycle. For
example, a 3-bit bi-directional port that is simulated for four cycles can have the following
data file:
ZZZ
110
011
XXX
Simulation returns an error if it cannot locate the specified data file.