Compiling hardware for use in M-Hwcosim follows the same flow as the typical Model Composer HDL hardware co-simulation flow.
- Start with a Model Composer model in Simulink.
- Select a hardware co-simulation target in the Compiling Hardware for Use with M-Hwcosim.
- Click Generate. This creates a hardware co-simulation library.
At the end of the generation, a hardware co-simulation library is created.
Among other files in the netlist directory, you can find a bit file and an hwc file. The bit file corresponds to the FPGA implementation, and the hwc file contains information required for M-Hwcosim. Both bit file and hwc file are paired by name, for example, mydesign_cw.bit and mydesign_cw.hwc.
The hwc file specifies additional meta information for describing the design and the chosen hardware co-simulation interface. Using the meta information, you can instantiate a hardware co-simulation instance with M-Hwcosim and interact with the co-simulation engine.
M-Hwcosim inherits the same concepts of ports and fixed point notations as found in the existing co-simulation block. Every design exposes its top-level ports for external access.