Vitis Model Composer can compile your design into an equivalent, lower level representation in several ways. How it compiles a design depends on settings in the Model Composer Hub block dialog box. The support for different compilation types provides you the freedom to choose a suitable representation for your design's environment. For example, an HDL Netlist or IP catalog is an appropriate target if your design is a component in a larger system.
| HDL Netlist Compilation | Describes how to generate HDL files that implement the design. |
| Hardware Co-Simulation Compilation | Describes how to configure Model Composer to compile your design into FPGA hardware for use by Simulink® and Questa. |
| IP Catalog Compilation |
Describes how to package a Model Composer design as an IP core that can be added to the AMD Vivado™ IP catalog for use in another design. Model Composer uses the IP catalog compilation type as the default generation target. |
| Synthesized Checkpoint Compilation | Describes how to generate a
synthesized checkpoint file (synth_1.dcp) for use in a Vivado integrated design environment (IDE) project. |
| Vitis Subsystem Compilation | Describes how to encapsulate a design consisting of HDL, HLS, and/or AI Engine components into a Vitis Subsystem. |